专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06292420B1 Method and device for automatically performing refresh operation in semiconductor memory device 有权
标题翻译：用于在半导体存储器件中自动执行刷新操作的方法和装置
公开(公告)号：US06292420B1
公开(公告)日：2001-09-18
申请号：US09604300
申请日：2000-06-26
申请人： Kang Yong Kim , Saeng Hwan Kim , Jong Hee Han
发明人： Kang Yong Kim , Saeng Hwan Kim , Jong Hee Han
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： The present invention discloses a method and a device for automatically performing a refresh operation, which can reduce power consumption in an auto refresh mode of a semiconductor memory device. The power consumption can be reduced by controlling the operation of input buffers or the operation of an input buffer generator for controlling the input buffers, during the auto refresh operation. The device for automatically performing the refresh operation in the semiconductor memory device, includes: a plurality of input buffers; an input buffer generator for controlling the operation of the plurality of input buffers; a command decoder for decoding a signal from one input buffer among the plurality of input buffers, and generating an auto refresh signal; a row active generator for generating a row active signal as the auto refresh signal is enabled; a delay generator for generating a delay signal delayed as long as a RAS cycle time according to the row active signal; and an auto refresh generator for controlling the plurality of input buffers by employing a control signal decided by the combination of the auto refresh signal from the command decoder and the delay signal from the delay generator.
摘要翻译：本发明公开了一种自动执行刷新操作的方法和装置，其可以降低半导体存储器件的自动刷新模式中的功耗。在自动刷新操作期间，通过控制输入缓冲器的操作或用于控制输入缓冲器的输入缓冲发生器的操作，能够降低功耗。用于在半导体存储器件中自动执行刷新操作的装置包括：多个输入缓冲器; 用于控制多个输入缓冲器的操作的输入缓冲器发生器; 命令解码器，用于对来自多个输入缓冲器中的一个输入缓冲器的信号进行解码，并产生自动刷新信号; 用于在启用自动刷新信号时产生行有源信号的行有源发生器; 延迟发生器，用于根据行有效信号产生延迟RAS周期时间的延迟信号; 以及自动刷新发生器，用于通过采用由命令解码器的自动刷新信号和来自延迟发生器的延迟信号的组合决定的控制信号来控制多个输入缓冲器。

2. 发明授权

US08638597B2 Bit line charge accumulation sensing for resistive changing memory 有权
标题翻译：电阻变化存储器的位线电荷累积检测
公开(公告)号：US08638597B2
公开(公告)日：2014-01-28
申请号：US13476368
申请日：2012-05-21
申请人： Chulmin Jung , Yong Lu , Kang Yong Kim , Young Pil Kim
发明人： Chulmin Jung , Yong Lu , Kang Yong Kim , Young Pil Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/14 , G11C7/02 , G11C7/04 , G11C7/062 , G11C11/1673
摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.
摘要翻译：存储器阵列包括多个磁阻改变存储单元。每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。字线电耦合到门。还公开了用于磁阻改变存储器的位线电荷累积感测。

3. 发明申请

US20120230094A1 BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY 有权
标题翻译：用于电阻变化存储器的位线电荷累积感测
公开(公告)号：US20120230094A1
公开(公告)日：2012-09-13
申请号：US13476368
申请日：2012-05-21
申请人： Chulmin Jung , Yong Lu , Kang Yong Kim , Young Pil Kim
发明人： Chulmin Jung , Yong Lu , Kang Yong Kim , Young Pil Kim
IPC分类号： G11C11/16
CPC分类号： G11C7/14 , G11C7/02 , G11C7/04 , G11C7/062 , G11C11/1673
摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.
摘要翻译：存储器阵列包括多个磁阻改变存储单元。每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。字线电耦合到门。还公开了用于磁阻改变存储器的位线电荷累积感测。

4. 发明授权

US07898308B2 Apparatus and method for trimming static delay of a synchronizing circuit 有权
标题翻译：用于修整同步电路的静态延迟的装置和方法
公开(公告)号：US07898308B2
公开(公告)日：2011-03-01
申请号：US12699625
申请日：2010-02-03
申请人： Tyler Gomm , Kang Yong Kim
发明人： Tyler Gomm , Kang Yong Kim
IPC分类号： H03L7/06
CPC分类号： G11C29/02 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0812
摘要： A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.
摘要翻译：一种用于修整延迟锁定环（DLL）的未经调整的前向延迟并修剪由DLL提供的第一和第二输出时钟信号的占空比的系统和方法。为了调整未调整的正向延迟，将延迟添加到反馈时钟信号路径和输入时钟信号路径之一，并且从反馈时钟信号路径提供反馈时钟信号，并且从输入时钟信号路径提供输入时钟信号进行相位比较。为了调整第一和第二输出时钟信号的占空比，第一延迟输入时钟信号和第二延迟输入时钟信号之一被延迟。第一和第二延迟输入时钟信号是互补的。延迟的时钟信号和另一个时钟信号被提供为第一和第二输出时钟信号。

5. 发明申请

US20100177577A1 SIGNAL TRANSFER APPARATUS AND METHODS 有权
标题翻译：信号传输装置和方法
公开(公告)号：US20100177577A1
公开(公告)日：2010-07-15
申请号：US12730994
申请日：2010-03-24
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/103 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括被配置为接收多个信号的多个节点。信号可以表示存储在诸如存储器装置的装置的多个存储单元中的信息。该设备可以包括多个传输路径，其具有耦合在节点和输出节点之间的存储元件。传输路径可以被配置为经由传输路径之一将信号的选定信号从节点之一传送到输出节点。传送路径可以被配置为仅将所选信号的值保存在仅一个存储元件中。每个传送路径可以仅包括一个存储元件。公开了包括附加装置，系统和方法的其它实施例。

6. 发明申请

US20100045341A1 Method and Apparatus for High Resolution ZQ Calibration 有权
标题翻译：高分辨率ZQ校准方法与装置
公开(公告)号：US20100045341A1
公开(公告)日：2010-02-25
申请号：US12613632
申请日：2009-11-06
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0278
摘要： A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种用于控制具有要连接外部负载的阻抗控制端子的类型的电子设备的输出阻抗的方法，使得阻抗控制端子处的电压的预定值控制该设备的输出阻抗。该方法包括将参考电压与阻抗控制端子处的电压进行比较。响应于比较而产生表示计数值的可变计数信号。可变阻抗电路的阻抗响应于计数信号而变化，其中可变阻抗电路的阻抗控制阻抗控制端子处的电压。周期性地操作与可变阻抗电路并联连接的装置，以改变（增加/减少）可变阻抗电路的阻抗。还公开了一种用于执行该方法的装置。

7. 发明授权

US07626416B2 Method and apparatus for high resolution ZQ calibration 有权
标题翻译：用于高分辨率ZQ校准的方法和装置
公开(公告)号：US07626416B2
公开(公告)日：2009-12-01
申请号：US11299888
申请日：2005-12-12
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： H03K17/16 , H03K19/003 , G11C7/10
CPC分类号： H03K19/0005 , H04L25/0278
摘要： A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种用于控制具有要连接外部负载的阻抗控制端子的类型的电子设备的输出阻抗的方法，使得阻抗控制端子处的电压的预定值控制该设备的输出阻抗。该方法包括将参考电压与阻抗控制端子处的电压进行比较。响应于比较而产生表示计数值的可变计数信号。可变阻抗电路的阻抗响应于计数信号而变化，其中可变阻抗电路的阻抗控制阻抗控制端子处的电压。周期性地操作与可变阻抗电路并联连接的装置，以改变（增加/减少）可变阻抗电路的阻抗。还公开了一种用于执行该方法的装置。

8. 发明授权

US07489568B2 Delay stage-interweaved analog DLL/PLL 有权
标题翻译：延迟级交织模拟DLL / PLL
公开(公告)号：US07489568B2
公开(公告)日：2009-02-10
申请号：US11297184
申请日：2005-12-08
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种使得可以根据可能取决于输入参考时钟的频率的操作条件对模拟延迟锁定环（DLL）或锁相环（PLL）的延迟级进行编程的方法。所产生的优化延迟级允许宽的频率范围的操作，在宽的输入时钟频率范围内的快速锁定时间以及在高时钟频率下的较低的电流消耗。通过允许在给定操作期间激活的模拟延迟级的数量被灵活地设置来实现更好的性能。未使用的延迟级的停用或关闭在较高频率下节省功率。通过为各种输入时钟频率使用灵活数量的延迟级来增加操作的高频范围。由于管理摘要的规则，本摘要不应用于解释索赔。

9. 发明授权

US07417478B2 Delay line circuit 有权
标题翻译：延迟线电路
公开(公告)号：US07417478B2
公开(公告)日：2008-08-26
申请号：US11349397
申请日：2006-02-06
申请人： Kang Yong Kim , Jongtae Kwak
发明人： Kang Yong Kim , Jongtae Kwak
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222
摘要： Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay units, among the delay units, are coupled to an even clock line to generate a first intermediate clock. Odd delay units are coupled to an odd clock line to generate a second intermediate clock. The even and odd delay units are configured to in a manner intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
摘要翻译：提供了方法，电路，设备和系统，包括用于延迟锁定环路的延迟线。一种方法包括向延迟线中的第一延迟单元提供参考时钟。延迟线包括耦合在一起的多个延迟单元。延迟单元中的偶数延迟单元耦合到偶数时钟线以产生第一中间时钟。奇数延迟单元耦合到奇数时钟线以产生第二中间时钟。偶数和奇数延迟单元被配置为以附加延迟单元耦合到延迟单元的数量来限制驱动与负载比的增加以及固有延迟。

10. 发明申请

US20080136475A1 Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage 有权
标题翻译：使用线路入口点控制可变延迟线来修改线路电源电压
公开(公告)号：US20080136475A1
公开(公告)日：2008-06-12
申请号：US11608903
申请日：2006-12-11
申请人： Tyler Gomm , Kang Yong Kim , Jongtae Kwak
发明人： Tyler Gomm , Kang Yong Kim , Jongtae Kwak
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/0814
摘要： Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.
摘要翻译：本文公开了一种VDL / DLL架构，其中至少将VDL，VccVDL的电源调节为输入信号（ClkIn）入口到VDL中的函数。具体地说，当通过VDL的延迟相对较小（当入口点朝向VDL的右侧（或最小延迟）边缘）时，VccVDL被调节为较高，并且当延迟相对较高时（当入口点朝向VDL的左侧（或最大延迟）边缘）。这提供了在VDL的各个阶段的分级延迟，但是不需要分别设计每个阶段。其他优点包括可在更宽的频率范围内操作的VDL / DLL设计，以及减少的级数，包括减少数量的缓冲级。此外，当使用所公开的技术时，可以完全省去缓冲阶段。另外，所公开的VDL架构可以用于可能有利的是通过作为VDL入口点的函数的可变延迟来延迟信号的任何情况。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式