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1. 发明授权

US07489568B2 Delay stage-interweaved analog DLL/PLL 有权
标题翻译：延迟级交织模拟DLL / PLL
公开(公告)号：US07489568B2
公开(公告)日：2009-02-10
申请号：US11297184
申请日：2005-12-08
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种使得可以根据可能取决于输入参考时钟的频率的操作条件对模拟延迟锁定环（DLL）或锁相环（PLL）的延迟级进行编程的方法。所产生的优化延迟级允许宽的频率范围的操作，在宽的输入时钟频率范围内的快速锁定时间以及在高时钟频率下的较低的电流消耗。通过允许在给定操作期间激活的模拟延迟级的数量被灵活地设置来实现更好的性能。未使用的延迟级的停用或关闭在较高频率下节省功率。通过为各种输入时钟频率使用灵活数量的延迟级来增加操作的高频范围。由于管理摘要的规则，本摘要不应用于解释索赔。

2. 发明授权

US07835205B2 Delay stage-interweaved analog DLL/PLL 有权
标题翻译：延迟级交织模拟DLL / PLL
公开(公告)号：US07835205B2
公开(公告)日：2010-11-16
申请号：US12252618
申请日：2008-10-16
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种使得可以根据可能取决于输入参考时钟的频率的操作条件对模拟延迟锁定环（DLL）或锁相环（PLL）的延迟级进行编程的方法。所产生的优化延迟级允许宽的频率范围的操作，在宽的输入时钟频率范围内的快速锁定时间以及在高时钟频率下的较低的电流消耗。通过允许在给定操作期间激活的模拟延迟级的数量被灵活地设置来实现更好的性能。未使用的延迟级的停用或关闭在较高频率下节省功率。通过为各种输入时钟频率使用灵活数量的延迟级来增加操作的高频范围。由于管理摘要的规则，本摘要不应用于解释索赔。

3. 发明授权

US07447106B2 Delay stage-interweaved analog DLL/PLL 有权
公开(公告)号：US07447106B2
公开(公告)日：2008-11-04
申请号：US11297181
申请日：2005-12-08
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

4. 发明授权

US07382678B2 Delay stage-interweaved analog DLL/PLL 有权
标题翻译：延迟级交织模拟DLL / PLL
公开(公告)号：US07382678B2
公开(公告)日：2008-06-03
申请号：US11297768
申请日：2005-12-08
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种使得可以根据可能取决于输入参考时钟的频率的操作条件对模拟延迟锁定环（DLL）或锁相环（PLL）的延迟级进行编程的方法。所产生的优化延迟级允许宽的频率范围的操作，在宽的输入时钟频率范围内的快速锁定时间以及在高时钟频率下的较低的电流消耗。通过允许在给定操作期间激活的模拟延迟级的数量被灵活地设置来实现更好的性能。未使用的延迟级的停用或关闭在较高频率下节省功率。通过为各种输入时钟频率使用灵活数量的延迟级来增加操作的高频范围。由于管理摘要的规则，本摘要不应用于解释索赔。

5. 发明申请

US20090066379A1 Delay Stage-Interweaved Analog DLL/PLL 有权
标题翻译：延迟阶段交织模拟DLL / PLL
公开(公告)号：US20090066379A1
公开(公告)日：2009-03-12
申请号：US12252618
申请日：2008-10-16
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种使得可以根据可能取决于输入参考时钟的频率的操作条件对模拟延迟锁定环（DLL）或锁相环（PLL）的延迟级进行编程的方法。所产生的优化延迟级允许宽的频率范围的操作，在宽的输入时钟频率范围内的快速锁定时间以及在高时钟频率下的较低的电流消耗。通过允许在给定操作期间激活的模拟延迟级的数量被灵活地设置来实现更好的性能。未使用的延迟级的停用或关闭在较高频率下节省功率。通过为各种输入时钟频率使用灵活数量的延迟级来增加操作的高频范围。由于管理摘要的规则，本摘要不应用于解释索赔。

6. 发明授权

US07149145B2 Delay stage-interweaved analog DLL/PLL 有权
公开(公告)号：US07149145B2
公开(公告)日：2006-12-12
申请号：US10893804
申请日：2004-07-19
申请人： Kang Yong Kim , Dong Myung Choi
发明人： Kang Yong Kim , Dong Myung Choi
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0802 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/10
摘要： A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

7. 发明授权

US08638597B2 Bit line charge accumulation sensing for resistive changing memory 有权
标题翻译：电阻变化存储器的位线电荷累积检测
公开(公告)号：US08638597B2
公开(公告)日：2014-01-28
申请号：US13476368
申请日：2012-05-21
申请人： Chulmin Jung , Yong Lu , Kang Yong Kim , Young Pil Kim
发明人： Chulmin Jung , Yong Lu , Kang Yong Kim , Young Pil Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/14 , G11C7/02 , G11C7/04 , G11C7/062 , G11C11/1673
摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.
摘要翻译：存储器阵列包括多个磁阻改变存储单元。每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。字线电耦合到门。还公开了用于磁阻改变存储器的位线电荷累积感测。

8. 发明申请

US20120230094A1 BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY 有权
标题翻译：用于电阻变化存储器的位线电荷累积感测
公开(公告)号：US20120230094A1
公开(公告)日：2012-09-13
申请号：US13476368
申请日：2012-05-21
申请人： Chulmin Jung , Yong Lu , Kang Yong Kim , Young Pil Kim
发明人： Chulmin Jung , Yong Lu , Kang Yong Kim , Young Pil Kim
IPC分类号： G11C11/16
CPC分类号： G11C7/14 , G11C7/02 , G11C7/04 , G11C7/062 , G11C11/1673
摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.
摘要翻译：存储器阵列包括多个磁阻改变存储单元。每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。字线电耦合到门。还公开了用于磁阻改变存储器的位线电荷累积感测。

9. 发明授权

US07898308B2 Apparatus and method for trimming static delay of a synchronizing circuit 有权
标题翻译：用于修整同步电路的静态延迟的装置和方法
公开(公告)号：US07898308B2
公开(公告)日：2011-03-01
申请号：US12699625
申请日：2010-02-03
申请人： Tyler Gomm , Kang Yong Kim
发明人： Tyler Gomm , Kang Yong Kim
IPC分类号： H03L7/06
CPC分类号： G11C29/02 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0812
摘要： A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.
摘要翻译：一种用于修整延迟锁定环（DLL）的未经调整的前向延迟并修剪由DLL提供的第一和第二输出时钟信号的占空比的系统和方法。为了调整未调整的正向延迟，将延迟添加到反馈时钟信号路径和输入时钟信号路径之一，并且从反馈时钟信号路径提供反馈时钟信号，并且从输入时钟信号路径提供输入时钟信号进行相位比较。为了调整第一和第二输出时钟信号的占空比，第一延迟输入时钟信号和第二延迟输入时钟信号之一被延迟。第一和第二延迟输入时钟信号是互补的。延迟的时钟信号和另一个时钟信号被提供为第一和第二输出时钟信号。

10. 发明申请

US20100177577A1 SIGNAL TRANSFER APPARATUS AND METHODS 有权
标题翻译：信号传输装置和方法
公开(公告)号：US20100177577A1
公开(公告)日：2010-07-15
申请号：US12730994
申请日：2010-03-24
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/103 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括被配置为接收多个信号的多个节点。信号可以表示存储在诸如存储器装置的装置的多个存储单元中的信息。该设备可以包括多个传输路径，其具有耦合在节点和输出节点之间的存储元件。传输路径可以被配置为经由传输路径之一将信号的选定信号从节点之一传送到输出节点。传送路径可以被配置为仅将所选信号的值保存在仅一个存储元件中。每个传送路径可以仅包括一个存储元件。公开了包括附加装置，系统和方法的其它实施例。

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