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    • 3. 发明授权
    • Circuitry for and method of generating vertical drive pulse in video
signal receiver
    • 在视频信号接收机中产生垂直驱动脉冲的电路和方法
    • US4897723A
    • 1990-01-30
    • US352524
    • 1989-05-16
    • Hiromi Arai
    • Hiromi Arai
    • H04N5/12
    • H04N5/12
    • The vertical drive pulse generator comprises a gate (59) passing a vertical synchronizing signal included in received video signals in response to a control signal, a counter (60; 360) counting a clock signal (CL) of 2f.sub.H (f.sub.H : a frequency of a horizontal synchronizing signal) to generate a plurality of timing signals, a 50/60 decider (65; 365) deciding whether the vertical synchronizing signal from the gate is of the NTSC or the PAL system and a synchronization decoder (66; 366) detecting whether the counter is reset in response to the vertical synchronizing signal passed through the gate or by a timing signal outputted by itself. One of the timing signals from the counter is selected in response to the outputs of the 50/60 decider (365; 65) and the synchronization detector (66; 366) and applied to the gate, thereby to make the gate pass a signal only when the control signal is received. When the 50/60 decider indicates that the arriving vertical synchronizing signal is of the NTSC system, the gate circuit (67; 367) opens during a period of 224 H to 296 H (H: a horizontal scanning period), while detecting the PAL system to open the gate during a period of 268 H to 356 H. when a step-out detection circuit (66; 366) detects a step-out state, the gate opens during 224 H to 356 H. The vertical drive pulse generator further comprises a phase comparator (422) which selects and generates a signal for defining a gate period of either 260.5 H to 264 H for NTSC system or 310.5 H to 314 H for PAL system.
    • 5. 发明授权
    • Sync detection circuit
    • 同步检测电路
    • US4814878A
    • 1989-03-21
    • US74605
    • 1987-07-17
    • Hiroyasu KishiHiromi Arai
    • Hiroyasu KishiHiromi Arai
    • H04N5/05H04N5/12H04N5/08
    • H04N5/12H04N5/05
    • A sync detection circuit detects a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with the repetition period other than the predetermined repetition period, and a signal absent condition which occurs when the broadcasting is finished. The sync detection circuit includes a V-sync separator for separating V-sync signals, a counter for counting the predetermined repetition period in relation to each of the V-sync signals and for producing a count-up signal upon counting the predetermined repetition period, and a phase comparator for comparing the phase of the count-up signal with the phase of a V-sync signal and for producing a first level signal, representing the receipt of the standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of the nonstandard signal, when the compared signals have the different phase. The counter also counts a predetermined time period, which is greater than the predetermined repetition period, in relation to the V-sync signal and for producing a time-up signal upon counting the predetermined time period, and a condition detector for detecting the signal absent condition when no V-sync signal appears before the time-up signal is produced.
    • 7. 发明授权
    • Vertical driving pulse generating circuit
    • 垂直驱动脉冲发生电路
    • US4845563A
    • 1989-07-04
    • US63949
    • 1987-06-19
    • Hiroyasu KishiHiromi Arai
    • Hiroyasu KishiHiromi Arai
    • H04N5/12
    • H04N5/12
    • A reset pulse having a desired pulse width is generated in a reset pulse generating circuit 14 in response to a vertical synchronizing signal selected and outputted from input selecting circuit 13 or a frequency-divided output signal of a vertical count down circuit 11, the vertical count down circuit 11 is reset by the reset pulse, and a vertical driving pulse .phi..sub.5 with a predetermined period is generated. Furthermore, phases of the reset pulse and the frequency-divided output signal are compared in a phase comparing circuit 19, a period of a vertical synchronizing signal is determined, and the input selecting circuit 13 and a signal selecting circuit 18 are switched to each other in accordance with the result.
    • 响应于从输入选择电路13选择并输出的垂直同步信号或垂直倒数电路11的分频输出信号,在复位脉冲发生电路14中生成具有期望脉冲宽度的复位脉冲,垂直计数 下降电路11由复位脉冲复位,并且产生具有预定周期的垂直驱动脉冲phi 5。 此外,在相位比较电路19中比较复位脉冲和分频输出信号的相位,确定垂直同步信号的周期,并且输入选择电路13和信号选择电路18彼此切换 按照结果。