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1. 发明申请

US20080290401A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICES WITH CHARGE INJECTION CORNER 有权
标题翻译：带电荷注射角的非线性半导体存储器件
公开(公告)号：US20080290401A1
公开(公告)日：2008-11-27
申请号：US12124143
申请日：2008-05-20
申请人： Kan YASUI , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
发明人： Kan YASUI , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/11526 , H01L27/11546 , H01L29/42344
摘要： An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.
摘要翻译：在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。

2. 发明授权

US07915666B2 Nonvolatile semiconductor memory devices with charge injection corner 有权
标题翻译：具有电荷注入角的非易失性半导体存储器件
公开(公告)号：US07915666B2
公开(公告)日：2011-03-29
申请号：US12124143
申请日：2008-05-20
申请人： Kan Yasui , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
发明人： Kan Yasui , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/11526 , H01L27/11546 , H01L29/42344
摘要： An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.
摘要翻译：在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。

3. 发明授权

US07935597B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07935597B2
公开(公告)日：2011-05-03
申请号：US12912609
申请日：2010-10-26
申请人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
发明人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0425 , H01L21/28282 , H01L21/31155 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.
摘要翻译：提高了包括非易失性存储器的半导体器件的性能和可靠性。非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极存储功能。第一电介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层电介质膜。位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

4. 发明授权

US07872298B2 Split-gate type memory device 有权
标题翻译：分闸式存储装置
公开(公告)号：US07872298B2
公开(公告)日：2011-01-18
申请号：US11777812
申请日：2007-07-13
申请人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
发明人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , G11C16/0425 , H01L21/28282 , H01L21/31155 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.
摘要翻译：提高了包括非易失性存储器的半导体器件的性能和可靠性。非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极存储功能。第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层电介质膜。位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

5. 发明申请

US20080048249A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080048249A1
公开(公告)日：2008-02-28
申请号：US11773842
申请日：2007-07-05
申请人： NAOKI TEGA , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
发明人： NAOKI TEGA , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L29/42324 , H01L29/4234 , H01L29/42344 , H01L29/66833
摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.
摘要翻译：在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置栅极绝缘膜（d> = 0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近连续平滑地接合。通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

6. 发明申请

US20110039385A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110039385A1
公开(公告)日：2011-02-17
申请号：US12912609
申请日：2010-10-26
申请人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
发明人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0425 , H01L21/28282 , H01L21/31155 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.
摘要翻译：提高了包括非易失性存储器的半导体器件的性能和可靠性。非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极存储功能。第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层电介质膜。位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

7. 发明授权

US07709315B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07709315B2
公开(公告)日：2010-05-04
申请号：US11773842
申请日：2007-07-05
申请人： Naoki Tega , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
发明人： Naoki Tega , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L29/42324 , H01L29/4234 , H01L29/42344 , H01L29/66833
摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.
摘要翻译：在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置栅极绝缘膜（d≥0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近依次平滑地接合。通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

8. 发明授权

US08063433B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08063433B2
公开(公告)日：2011-11-22
申请号：US12109340
申请日：2008-04-24
申请人： Tetsuya Ishimaru , Yasuhiro Shimamoto , Toshiyuki Mine , Yasunobu Aoki , Koichi Toba , Kan Yasui
发明人： Tetsuya Ishimaru , Yasuhiro Shimamoto , Toshiyuki Mine , Yasunobu Aoki , Koichi Toba , Kan Yasui
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42344 , H01L29/513 , H01L29/66833
摘要： A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm−3 or less.
摘要翻译：存储单元包括由作为电荷捕获部分的氮化硅膜SIN和位于氮化硅膜下面的氧化物膜BOTOX和TOPOX的叠层膜，ONO膜上的存储栅电极MG，源区MS和漏区MD，并且通过在存储单元中的热载流子注入来执行编程或擦除。在存储单元中，氮化硅膜SIN中包含的N-H键和Si-H键的总浓度为5×10 20 cm -3以下。

9. 发明授权

US08796756B2 Nonvolatile semiconductor device and method of manufacturing the same 有权
标题翻译：非易失性半导体器件及其制造方法
公开(公告)号：US08796756B2
公开(公告)日：2014-08-05
申请号：US13755348
申请日：2013-01-31
申请人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasafumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
发明人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasafumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.
摘要翻译：插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为小于40nm。因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

10. 发明授权

US08125012B2 Non-volatile memory device with a silicon nitride charge holding film having an excess of silicon 有权
标题翻译：具有氮化硅电荷保持膜的非易失性存储器件具有过量的硅
公开(公告)号：US08125012B2
公开(公告)日：2012-02-28
申请号：US11639134
申请日：2006-12-15
申请人： Toshiyuki Mine , Kan Yasui , Tetsuya Ishimaru , Yasuhiro Shimamoto
发明人： Toshiyuki Mine , Kan Yasui , Tetsuya Ishimaru , Yasuhiro Shimamoto
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L29/42344 , H01L29/512 , H01L29/513 , H01L29/792 , Y10S438/954
摘要： Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.
摘要翻译：通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

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