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1. 发明授权

US07089485B2 Simple link protocol providing low overhead coding for LAN serial and WDM solutions 有权
标题翻译：简单的链路协议，为LAN串行和WDM解决方案提供低开销编码
公开(公告)号：US07089485B2
公开(公告)日：2006-08-08
申请号：US09776175
申请日：2001-02-02
申请人： Kamran Azadet , Leilei Song , Thomas E. Truman , Meng-Lin Yu
发明人： Kamran Azadet , Leilei Song , Thomas E. Truman , Meng-Lin Yu
IPC分类号： G06F11/00
CPC分类号： H04L1/0061 , H04J14/02 , H04L29/06 , H04L69/324
摘要： A data structure, method and protocol wherein synchronization data indicative of a data frame delineation point is inserted within an inter-packet gap (IPG) proximate a data frame during transmission. Optionally, a cyclical redundancy check (CRC) length indicative data, pointer data, and other data is inserted within the IPG to further insure appropriate delineation of data frames within a data stream.
摘要翻译：数据结构，方法和协议，其中指示数据帧描绘点的同步数据被插入在传输期间靠近数据帧的分组间间隔（IPG）内。可选地，在IPG内插入指示数据，指针数据和其他数据的循环冗余校验（CRC）长度，以进一步确保数据流内的数据帧的适当描述。

2. 发明申请

US20050210353A1 High speed syndrome-based FEC encoder and system using same 有权
标题翻译：基于高速综合征的FEC编码器和系统使用相同
公开(公告)号：US20050210353A1
公开(公告)日：2005-09-22
申请号：US11129193
申请日：2005-05-13
申请人： Ralf Dohmen , Timo Schuering , Leilei Song , Meng-Lin Yu
发明人： Ralf Dohmen , Timo Schuering , Leilei Song , Meng-Lin Yu
IPC分类号： H03M13/15 , H04L1/00 , G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00
CPC分类号： H03M13/1595 , H03M13/1515 , H03M13/1535 , H03M13/158
摘要： A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.
摘要翻译：公开了一种解码器，编码器和对应系统，用于提供基于错误校正码的纠错码的快速前向纠错（FEC）解码和编码。三并行处理由系统的元件执行。更具体地，在说明性实施例中，解码器执行三并行校正子生成和错误确定和计算，并且编码器执行三并行编码。低功耗和复杂度技术用于节省成本和功耗，同时提供相对高速的编码和解码。

3. 发明授权

US07254771B1 Error-erasure decoding of interleaved reed-solomon code 失效
标题翻译：交织的芦苇码的错误解码解码
公开(公告)号：US07254771B1
公开(公告)日：2007-08-07
申请号：US09577177
申请日：2000-05-23
申请人： Leilei Song , Meng-Lin Yu
发明人： Leilei Song , Meng-Lin Yu
IPC分类号： H03M13/00
CPC分类号： H03M13/154 , H03M13/2954 , H03M13/6561
摘要： A method of decoding interleaved Reed-Solomon codes to achieve an improved performance for burst errors is described. The method takes advantage of both interleaving and erasure decoding to increase the error correcting capability of a system without necessarily depending on channel reliability information. The observed correlation of burst errors in interleaved systems is advantageously used to achieve an improved error-correcting system, wherein a first code word is decoded, and the error locations in the first codeword are used to determine erasures for the remaining code words in the same interleaving block, and finally, decoding the remaining code words in parallel.
摘要翻译：描述了对交错的里德 - 所罗门码进行解码以实现突发错误的改进性能的方法。该方法利用交织和擦除解码来增加系统的纠错能力，而不必依赖于信道可靠性信息。观察到交织系统中突发错误的相关性有利地用于实现改进的纠错系统，其中第一码字被解码，并且第一码字中的错误位置被用于确定相同的剩余码字的擦除交织块，最后并行解码剩余码字。

4. 发明授权

US07085794B2 Low power vector summation method and apparatus 失效
公开(公告)号：US07085794B2
公开(公告)日：2006-08-01
申请号：US10122997
申请日：2002-04-12
申请人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
发明人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
IPC分类号： G06F7/38 , G06F17/10
CPC分类号： G06F7/5443 , G06F7/49994 , H03H17/0233 , H03H17/06
摘要： An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

5. 发明申请

US20140108477A1 VECTOR PROCESSOR HAVING INSTRUCTION SET WITH VECTOR CONVOLUTION FUNCTION FOR FIR FILTERING 有权
标题翻译：矢量处理器具有用于FIR滤波的矢量转换功能的指令
公开(公告)号：US20140108477A1
公开(公告)日：2014-04-17
申请号：US13701376
申请日：2012-10-26
申请人： Kameran Azadet , Meng-Lin Yu , Joseph H. Othmer , Joseph Williams , Albert Molina
发明人： Kameran Azadet , Meng-Lin Yu , Joseph H. Othmer , Joseph Williams , Albert Molina
IPC分类号： G06F5/01
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ni coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.
摘要翻译：提供了具有具有向量卷积函数的指令集的向量处理器。所公开的向量处理器通过获得包括至少N1 + N2-1个输入样本的向量来执行输入信号和滤波器脉冲响应之间的卷积函数; 获得矢量的N2时移版本（包括零位版本），其中每个时移版本包括Ni样本; 以及通过Ni系数的向量来执行向量的时移版本的加权和; 以及产生包括每个加权和的一个输出值的输出向量。矢量处理器例如响应于具有矢量输入的一个或多个向量卷积软件指令来执行该方法。矢量可以包括多个实数或复数输入样本，并且可以使用实数或复数的多个系数来表示滤波器脉冲响应。

6. 发明授权

US07328227B2 Low power vector summation apparatus 有权
标题翻译：低功率矢量求和装置
公开(公告)号：US07328227B2
公开(公告)日：2008-02-05
申请号：US11359201
申请日：2006-02-22
申请人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
发明人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
IPC分类号： G06F7/00
CPC分类号： G06F7/5443 , G06F7/49994 , H03H17/0233 , H03H17/06
摘要： An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
摘要翻译：提供了一种低功率矢量求和装置，用于使用2的补码运算而没有现有技术的高切换活动。特别地，本发明操作以利用2的补码的符号扩展属性。提供2的补码减少的表示，以避免符号扩展和符号扩展位的切换。检测2的补码的最大幅度，并动态生成其缩小表示以表示信号。通过缩小表示引入的恒定误差也被动态补偿。

7. 发明申请

US20060143259A1 Low power vector summation method and apparatus 有权
公开(公告)号：US20060143259A1
公开(公告)日：2006-06-29
申请号：US11359201
申请日：2006-02-22
申请人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
发明人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F7/49994 , H03H17/0233 , H03H17/06
摘要： An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

8. 发明授权

US06192072B1 Parallel processing decision-feedback equalizer (DFE) with look-ahead processing 有权
标题翻译：并行处理决策反馈均衡器（DFE）与前瞻处理
公开(公告)号：US06192072B1
公开(公告)日：2001-02-20
申请号：US09326781
申请日：1999-06-04
申请人： Kameran Azadet , Meng-Lin Yu
发明人： Kameran Azadet , Meng-Lin Yu
IPC分类号： H03H730
CPC分类号： H04L25/03057 , H04L2025/0349
摘要： A method and apparatus are disclosed for increasing the effective processing speed of a parallel decision-feedback equalizer (DFE) by combining block processing and look-ahead techniques in the selection (multiplexing) stage. The present invention extends a parallel DFE by using look-ahead techniques in the selection stage to precompute the effect of previous blocks on each subsequent block, and to thereby remove the serial output dependency. The parallel DFE includes a multiplexor tree structure that selects an appropriate output value for each block and precomputes the effect of previous blocks on each subsequent block. A multiplexing delay algorithm on the order of logN is employed to resolve the output dependency and thus speeds up parallel block processing DFEs. The disclosed DFE architecture can be combined with pipelining to completely eliminate the critical path problem. Pipelining reduces the required critical path timing to one multiplexing time. The disclosed multiplexor tree circuitry for the parallel DFE groups multiplexor blocks into groups of two, referred to as block pairs, and provides at least one multiplexor for each block, i, to select an output value, yi, from among the possible precomputed values. The output of each parallel block depends on the possible precomputed values generated by the look-ahead processors for the block, as well as the actual values that are ultimately selected for each previous block. In order to reduce the delay in obtaining each actual output value, the present invention assumes that each block contains each possible value, and carries the assumption through to all subsequent blocks. Thus, the number of multiplexors required to select from among the possible values grows according to N·logN, where N is the block number.
摘要翻译：公开了一种用于通过在选择（复用）阶段中组合块处理和先行技术来增加并行判决反馈均衡器（DFE）的有效处理速度的方法和装置。本发明通过在选择阶段中使用先行技术来扩展并行DFE，以预先计算先前块对每个后续块的影响，从而消除串行输出依赖性。并行DFE包括多路复用器树结构，其为每个块选择适当的输出值，并且预先计算先前块在每个后续块上的影响。采用logN顺序的复用延迟算法来解决输出依赖关系，从而加快并行块处理DFE。所公开的DFE架构可以与流水线结合，以完全消除关键路径问题。流水线将所需的关键路径时序减少到一个复用时间。所公开的用于并行DFE组多路复用器的多路复用器树电路块分成两组，被称为块对，并且为每个块提供至少一个多路复用器，i从可能的预计算值中选择输出值yi。每个并行块的输出取决于由块的先行处理器生成的可能的预计算值，以及最终为每个先前块选择的实际值。为了减少获得每个实际输出值的延迟，本发明假设每个块包含每个可能的值，并将假设传递给所有后续块。因此，从可能值中选择的多路复用器的数量根据N.logN而增长，其中N是块号。

9. 发明授权

US5694423A Method and apparatus for detecting and correcting misconvergence of a blind equalizer 失效
标题翻译：用于检测和校正盲均衡器失会聚的方法和装置
公开(公告)号：US5694423A
公开(公告)日：1997-12-02
申请号：US692554
申请日：1996-08-06
申请人： Patrik Larsson , Meng-Lin Yu
发明人： Patrik Larsson , Meng-Lin Yu
IPC分类号： H03H21/00 , H04L25/03 , H03H7/30 , H03K5/159
CPC分类号： H03H21/0012 , H04L25/03044 , H04L25/0305 , H04L2025/03662
摘要： Convergence of blind fractionally spaced equalizers is improved, and misconvergence is corrected by training the equalizers to detect convergence of one adaptive filter, copying the tap weights of the converged adaptive filter to the other adaptive filters and shifting the tap weights of the other adaptive filters according to the expected phase difference between the respective filters. In a two-dimensional orthogonal modulation scheme the converged weights of a first filter are copied to a second filter and shifted .pi./2. For the two dimensional orthogonal modulation scheme, the probability of a proper convergence can be increased by choosing initial tap weights for the two adaptive filters with a 3.pi./4 phase difference.
摘要翻译：通过训练均衡器来检测一个自适应滤波器的收敛，将收敛的自适应滤波器的抽头复制到其他自适应滤波器并根据其他自适应滤波器的抽头权重进行移位，从而改善了盲分数均衡器的收敛达到相应滤波器之间的预期相位差。在二维正交调制方案中，将第一滤波器的收敛权重复制到第二滤波器并移位pi / 2。对于二维正交调制方案，可以通过选择具有3π/ 4相位差的两个自适应滤波器的初始抽头权重来增加适当收敛的概率。

10. 发明授权

US09362977B2 Incremental preamble detection 有权
标题翻译：增量前导码检测
公开(公告)号：US09362977B2
公开(公告)日：2016-06-07
申请号：US13566146
申请日：2012-08-03
申请人： Ivan Leonidovich Mazurenko , Alexander Alexandrovich Petyushko , Meng-Lin Yu , Jian-Guo Chen
发明人： Ivan Leonidovich Mazurenko , Alexander Alexandrovich Petyushko , Meng-Lin Yu , Jian-Guo Chen
IPC分类号： H04B1/7075 , H04L7/04
CPC分类号： H04B1/70755 , H04L7/042
摘要： In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.
摘要翻译：在一个实施例中，本发明是一种用于在无线通信网络中执行增量前导码检测的方法。该方法处理输入天线数据的不重叠块，其中每个块小于前导码长度，以检测所发送的前导码的签名。对于处理的每个块，块的码片与由无线网络使用的可能的签名相关联，以更新一组相关轮廓，每个轮廓包括多个轮廓值。此外，通过将更新的简档值与也为每个块更新的中间阈值进行比较来执行中间检测。在接收到最后的块之后，更新相关轮廓，并且通过将更新的简档值与最终的阈值进行比较来进行最终的前导码检测。检测是按增量执行的，以满足无线网络的延迟要求。

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