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1. 发明授权

US07085794B2 Low power vector summation method and apparatus 失效
公开(公告)号：US07085794B2
公开(公告)日：2006-08-01
申请号：US10122997
申请日：2002-04-12
申请人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
发明人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
IPC分类号： G06F7/38 , G06F17/10
CPC分类号： G06F7/5443 , G06F7/49994 , H03H17/0233 , H03H17/06
摘要： An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

2. 发明授权

US07328227B2 Low power vector summation apparatus 有权
标题翻译：低功率矢量求和装置
公开(公告)号：US07328227B2
公开(公告)日：2008-02-05
申请号：US11359201
申请日：2006-02-22
申请人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
发明人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
IPC分类号： G06F7/00
CPC分类号： G06F7/5443 , G06F7/49994 , H03H17/0233 , H03H17/06
摘要： An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
摘要翻译：提供了一种低功率矢量求和装置，用于使用2的补码运算而没有现有技术的高切换活动。特别地，本发明操作以利用2的补码的符号扩展属性。提供2的补码减少的表示，以避免符号扩展和符号扩展位的切换。检测2的补码的最大幅度，并动态生成其缩小表示以表示信号。通过缩小表示引入的恒定误差也被动态补偿。

3. 发明申请

US20060143259A1 Low power vector summation method and apparatus 有权
公开(公告)号：US20060143259A1
公开(公告)日：2006-06-29
申请号：US11359201
申请日：2006-02-22
申请人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
发明人： Kameran Azadet , Meng-Lin Yu , Zhan Yu
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F7/49994 , H03H17/0233 , H03H17/06
摘要： An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

4. 发明授权

US08989315B1 Methods, algorithms, software, circuits, architectures, and systems for improved communications over cyclostationary channels 有权
标题翻译：方法，算法，软件，电路，架构和系统，用于改善循环平稳通道的通信
公开(公告)号：US08989315B1
公开(公告)日：2015-03-24
申请号：US12709428
申请日：2010-02-19
申请人： Zhan Yu , Runsheng He
发明人： Zhan Yu , Runsheng He
IPC分类号： H04L27/22 , H04B1/38
CPC分类号： H04L1/0071 , H04B3/54 , H04B2203/5416 , H04L1/0072 , H04L25/022
摘要： Methods, software, receivers and systems for communicating information over a cyclostationary channel. The method generally includes interleaving sections of a control sequence with bits of the information. The software and receivers are generally configured to implement one or more aspects of the methods disclosed herein, and the systems generally include those that embody the inventive receivers disclosed herein. The present invention is particularly useful in powerline channels, where certain parameters (such as noise) have time-dependent or periodic variations in value. By distributing the control sequence, the incidence of carrier recovery is reduced, the likelihood of successful packet or frame transmissions is increased, and data may be more reliably communicated.
摘要翻译：用于通过循环平稳通道传送信息的方法，软件，接收器和系统。该方法通常包括用信息的比特交织控制序列的部分。软件和接收机通常被配置为实现本文公开的方法的一个或多个方面，并且系统通常包括体现本文公开的创造性接收器的系统。本发明在电力线通道中特别有用，其中某些参数（例如噪声）具有时间依赖性或周期性的变化。通过分配控制序列，减少了载波恢复的发生，增加了成功的分组或帧传输的可能性，并且可以更可靠地传送数据。

5. 发明授权

US08020069B1 Methods of supporting host CRC in data storage systems without RLL coding 有权
标题翻译：在没有RLL编码的数据存储系统中支持主机CRC的方法
公开(公告)号：US08020069B1
公开(公告)日：2011-09-13
申请号：US11810221
申请日：2007-06-05
申请人： Weishi Feng , Zhan Yu
发明人： Weishi Feng , Zhan Yu
IPC分类号： H03M13/00
CPC分类号： G11B20/1833 , G11B20/1866
摘要： A data dependent scrambler for a communications channel that receives a user data sequence including N symbols and host cyclic redundancy check (CRCU) bits comprises a data buffer that receives the user data sequence and the host CRCU bits. A seed finder generates a scrambling seed that is dependent upon the symbols in the user data sequence. A first scrambler receives the user data sequence from the data buffer and the scrambling seed from the seed finder and generates the scrambled user data sequence. A second scrambler generates a difference sequence that is based on the user data sequence and the scrambled user data sequence.
摘要翻译：用于接收包括N个符号和主机循环冗余校验（CRCU）位的用户数据序列的通信信道的数据相关扰频器包括接收用户数据序列和主机CRCU位的数据缓冲器。种子查找器产生取决于用户数据序列中的符号的加扰种子。第一加扰器从数据缓冲器和来自种子寻找器的加扰种子接收用户数据序列，并产生加扰的用户数据序列。第二扰频器产生基于用户数据序列和扰频用户数据序列的差分序列。

6. 发明授权

US08014483B2 Method of acquiring initial synchronization in impulse wireless communication and receiver 有权
标题翻译：在脉冲无线通信和接收机中获取初始同步的方法
公开(公告)号：US08014483B2
公开(公告)日：2011-09-06
申请号：US12092488
申请日：2005-11-04
申请人： Yew Soo Eng , Zhan Yu
发明人： Yew Soo Eng , Zhan Yu
IPC分类号： H04L7/02
CPC分类号： H04B1/7183 , H04B1/7172 , H04B1/7176 , H04L7/042 , H04L7/10 , H04L25/4902 , H04W48/08
摘要： A receiver in an impulse wireless communication. The receiver (300) includes a pulse-pair correlator (304) that receives a signal (316) and divides it into two signals for paths. One of the signals is input to signal multiplier (312) while another signal is delayed by a delay unit (310). The signal multiplier (312) multiplies the received signal (316) by a delayed signal (318). An integrator (314) integrates an output signal (322) over a designated period of time. An adding module (306) sums an output signal (324) from the integrator (314). An acquiring module (308) compares an summing-up output (326) from the adding module (306) with a predetermined threshold value to detect the existence of a transmitting-standard preamble.
摘要翻译：脉冲无线通信中的接收机。接收器（300）包括接收信号（316）并将其分成用于路径的两个信号的脉冲对相关器（304）。一个信号被输入到信号乘法器（312），而另一个信号被延迟单元（310）延迟。信号乘法器（312）将接收信号（316）乘以延迟信号（318）。积分器（314）在指定的时间段内积分输出信号（322）。加法模块（306）对来自积分器（314）的输出信号（324）求和。获取模块（308）将来自加法模块（306）的求和输出（326）与预定阈值进行比较，以检测发送标准前导码的存在。

7. 发明授权

US07808404B1 Method and apparatus for generating a seed set in a data dependent seed selector 有权
标题翻译：用于在数据依赖种子选择器中生成种子集的方法和装置
公开(公告)号：US07808404B1
公开(公告)日：2010-10-05
申请号：US11649038
申请日：2007-01-02
申请人： Zhan Yu
发明人： Zhan Yu
IPC分类号： H03M5/00
CPC分类号： G11B20/1426 , G11B20/10 , G11B20/10009 , G11B20/1866 , H03M5/145
摘要： A seed generator for a scrambler comprises a seed set identifier that identifies a seed set based on received user data symbols, which include a plurality of M-bit symbols. A seed selector selects a scrambling seed for the scrambler from the seed set based on Hamming distances between at least two of the M-bit symbols in the seed set.
摘要翻译：用于加扰器的种子生成器包括种子集标识符，其基于接收到的包括多个M位符号的用户数据符号识别种子集。种子选择器基于种子集中的至少两个M位符号之间的汉明距离从种子集合中选择加扰器的加扰种子。

8. 发明授权

US07249310B1 Error evaluator for inversionless Berlekamp-Massey algorithm in Reed-Solomon decoders 有权
标题翻译： Reed-Solomon解码器中无倒数Berlekamp-Massey算法的误差评估器
公开(公告)号：US07249310B1
公开(公告)日：2007-07-24
申请号：US11243283
申请日：2005-10-04
申请人： Weishi Feng , Zhan Yu
发明人： Weishi Feng , Zhan Yu
IPC分类号： H03M13/03
CPC分类号： H03M13/153 , H03M13/6502
摘要： An error correcting Reed-Solomon decoder includes an error locator polynomial generator that generates an error locator polynomial and a scratch polynomial based on an inversionless Berlekamp-Massey algorithm (iBMA). An error location finder communicates with the error locator polynomial generator and generates error locations. An error values finder communicates with the error locator polynomial generator and generates error values directly from the error locator polynomial and the scratch polynomial.
摘要翻译：纠错Reed-Solomon解码器包括基于无倒数Berlekamp-Massey算法（iBMA）生成误差定位多项式和临时多项式的误差定位多项式发生器。错误位置查找器与错误定位器多项式生成器通信并生成错误位置。错误值查找器与错误定位器多项式生成器通信，并直接从误差定位器多项式和临时多项式生成误差值。

9. 发明授权

US08533577B1 Universal parity encoder 有权
标题翻译：通用奇偶编码器
公开(公告)号：US08533577B1
公开(公告)日：2013-09-10
申请号：US13555860
申请日：2012-07-23
申请人： Weishi Feng , Zhan Yu
发明人： Weishi Feng , Zhan Yu
IPC分类号： G06F11/00
CPC分类号： H03M5/145 , H03M13/09 , H03M13/27 , H04L1/0041 , H04L1/0061 , H04L1/0071
摘要： A data encoding system includes an interleaving module, a generating module, and an insertion module. The interleaving module is configured to receive a data stream. The data stream includes a plurality of data blocks. The interleaving module is configured to, for each data block of a selected subset of the plurality of data blocks, swap positions of a pair of adjacent bits of the data block. The generating module is configured to (i) receive the data stream and (ii) for each of the plurality of data blocks, generate at least one corresponding error checking bit. The insertion module is configured to (i) receive the plurality of data blocks as modified by the interleaving module and (ii) generate an output data stream by inserting the at least one corresponding error checking bit into each one of the plurality of data blocks received from the interleaving module.
摘要翻译：数据编码系统包括交织模块，生成模块和插入模块。交织模块被配置为接收数据流。数据流包括多个数据块。交织模块被配置为对于多个数据块的所选子集的每个数据块，数据块的一对相邻位的交换位置。生成模块被配置为（i）接收数据流，并且（ii）对于多个数据块中的每一个，生成至少一个相应的错误校验位。插入模块被配置为（i）接收由交织模块修改的多个数据块，并且（ii）通过将至少一个对应的错误校验位插入到所接收的多个数据块中的每一个中来生成输出数据流从交织模块。

10. 发明授权

US08230314B1 Universal parity decoder 有权
标题翻译：通用奇偶解码器
公开(公告)号：US08230314B1
公开(公告)日：2012-07-24
申请号：US12156649
申请日：2008-06-03
申请人： Weishi Feng , Zhan Yu
发明人： Weishi Feng , Zhan Yu
IPC分类号： G06F11/00
CPC分类号： H03M5/145 , H03M13/09 , H03M13/27 , H04L1/0041 , H04L1/0061 , H04L1/0071
摘要： A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.
摘要翻译：用于数据流的数据编码系统包括交织模块，其将数据流接收为N位数据块，并且反转所选数据块的N位中的至少两个的位置。生成模块为每个N位数据块生成P个错误校验位。插入模块从生成模块接收P个错误校验位，并将P个错误校验位插入到从交错模块接收到的对应的数据块中。

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