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1. 发明申请

US20050283772A1 Determination of loop unrolling factor for software loops 审中-公开
标题翻译：确定软件循环的循环展开因子
公开(公告)号：US20050283772A1
公开(公告)日：2005-12-22
申请号：US10874614
申请日：2004-06-22
申请人： Kalyan Muthukumar , Jean-Francois Collard
发明人： Kalyan Muthukumar , Jean-Francois Collard
IPC分类号： G06F9/45
CPC分类号： G06F8/4452
摘要： Disclosed are embodiments of a method and system for calculating an unrolling factor for software loops. The unrolling factor may be calculated by applying a formula that takes into account issue constraints of a processor. The issue constraints may include the total issue width of the processor, and may also include individual issue constraints for each instruction type. The software loop may be unrolled by the calculated unrolling factor and may be software pipelined. Other embodiments are also described and claimed.
摘要翻译：公开了用于计算软件循环的展开因子的方法和系统的实施例。可以通过应用考虑到处理器的问题约束的公式来计算展开因子。问题约束可以包括处理器的总发行宽度，并且还可以包括针对每个指令类型的单独的问题约束。软件循环可以通过计算的展开因子展开，并且可以是软件流水线的。还描述和要求保护其他实施例。

2. 发明申请

US20050216899A1 Resource-aware scheduling for compilers 失效
标题翻译：编译器的资源感知调度
公开(公告)号：US20050216899A1
公开(公告)日：2005-09-29
申请号：US10809716
申请日：2004-03-24
申请人： Kalyan Muthukumar , Daniel Lavery , Gerolf Hoflehner , Chu-Cheow Lim , Jean-Francois Collard
发明人： Kalyan Muthukumar , Daniel Lavery , Gerolf Hoflehner , Chu-Cheow Lim , Jean-Francois Collard
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： Disclosed are embodiments of a compiler, methods, and system for resource-aware scheduling of instructions. A list scheduling approach is augmented to take into account resource constraints when determining priority for scheduling of instructions. Other embodiments are also described and claimed.
摘要翻译：公开了用于指令的资源感知调度的编译器，方法和系统的实施例。增加列表调度方法以在确定指令调度的优先级时考虑到资源约束。还描述和要求保护其他实施例。

3. 发明授权

US07617495B2 Resource-aware scheduling for compilers 失效
标题翻译：编译器的资源感知调度
公开(公告)号：US07617495B2
公开(公告)日：2009-11-10
申请号：US10809716
申请日：2004-03-24
申请人： Kalyan Muthukumar , Daniel M. Lavery , Gerolf F. Hoflehner , Chu-cheow Lim , Jean-Francois Collard
发明人： Kalyan Muthukumar , Daniel M. Lavery , Gerolf F. Hoflehner , Chu-cheow Lim , Jean-Francois Collard
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： Disclosed are embodiments of a compiler, methods, and system for resource-aware scheduling of instructions. A list scheduling approach is augmented to take into account resource constraints when determining priority for scheduling of instructions. Other embodiments are also described and claimed.
摘要翻译：公开了用于指令的资源感知调度的编译器，方法和系统的实施例。增加列表调度方法以在确定指令调度的优先级时考虑到资源约束。还描述和要求保护其他实施例。

4. 发明申请

US20150268711A1 Selecting A Low Power State Based On Cache Flush Latency Determination 有权
标题翻译：基于缓存冲突延迟确定选择低功耗状态
公开(公告)号：US20150268711A1
公开(公告)日：2015-09-24
申请号：US14221696
申请日：2014-03-21
申请人： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
发明人： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3296 , G06F12/0804 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/128 , G06F2212/1028 , G06F2212/314 , G06F2212/621 , G06F2212/69 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/152 , Y02D10/172 , Y02D50/20
摘要： In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核以独立地执行指令，耦合到核的共享高速缓存并且包括多条线来存储数据，以及包括低功率控制逻辑的功率控制器来计算冲洗等待时间所述共享高速缓存基于所述多条线路的状态。描述和要求保护其他实施例。

5. 发明申请

US20050071607A1 System, method, and apparatus for spilling and filling rotating registers in software-pipelined loops 失效
标题翻译：用于在软件流水线循环中溢出和填充旋转寄存器的系统，方法和装置
公开(公告)号：US20050071607A1
公开(公告)日：2005-03-31
申请号：US10673741
申请日：2003-09-29
申请人： Kalyan Muthukumar
发明人： Kalyan Muthukumar
IPC分类号： G06F9/30 , G06F9/45 , G06F15/00
CPC分类号： G06F9/3013 , G06F8/4452 , G06F9/30134
摘要： An efficient method for software-pipelining (SWP) of loops to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer. In one example embodiment, this is accomplished by spilling and filling multiple computed values, in a register, that are live across multiple stages in a software-pipelined loop, using multiple rotating stack memory locations to reduce compiler-time of SWP, and complexity of the implemented SWP.
摘要翻译：一种循环软件流水线（SWP）的有效方法，用于将程序从较高级别的语言翻译成等效对象或机器语言代码，以便在计算机上执行。在一个示例实施例中，这是通过使用多个旋转堆栈存储器位置溢出并填充在寄存器中的多个计算值来实现的，所述多个计算值在软件流水线循环中的多个阶段处于活动状态，以减少SWP的编译器时间和复杂度实施的SWP。

6. 发明授权

US08843775B2 Energy optimization techniques in a computing system 有权
标题翻译：计算系统中的能量优化技术
公开(公告)号：US08843775B2
公开(公告)日：2014-09-23
申请号：US13018810
申请日：2011-02-01
申请人： Kalyan Muthukumar , Seshadri Harinarayanan , Rama Kishan V. Malladi , Raghavendra S. Hebbalalu , Mukesh Gangadhar
发明人： Kalyan Muthukumar , Seshadri Harinarayanan , Rama Kishan V. Malladi , Raghavendra S. Hebbalalu , Mukesh Gangadhar
IPC分类号： G06F1/26 , G06F1/00 , G06F9/00
CPC分类号： G06F1/3206 , G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions.
摘要翻译：计算平台可以包括用于确定多个区域中的每一个的性能损失值和能量节省值和/或应用程序内的多个区域中的每一个的存储器有界值的组件。计算平台可以为用户提供用户界面以提供用户输入，其提供可接受的性能损失的指示。为了提供的性能损失值，可以确定频率值，并且可以在处理多个区域中的每个区域的同时以频率值操作处理元件。

7. 发明授权

US06912709B2 Mechanism to avoid explicit prologs in software pipelined do-while loops 失效
标题翻译：机制避免在软件流水线的do-while循环中的明确序言
公开(公告)号：US06912709B2
公开(公告)日：2005-06-28
申请号：US09753254
申请日：2000-12-29
申请人： David A Helder , Kalyan Muthukumar
发明人： David A Helder , Kalyan Muthukumar
IPC分类号： G06F9/30 , G06F9/44 , G06F9/48
CPC分类号： G06F9/4881
摘要： The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined loop is initialized with a speculative instruction deactivated. At least one initiation interval of the software-pipelined loop is executed, and the speculative instruction is activated. Subsequent initiation intervals of the software-pipelined loop are then executed.
摘要翻译：本发明提供了一种促进软件流水线循环内的指令执行的机制。根据本发明的一个实施例，软件流水线循环被初始化，推测性指令被禁用。执行软件流水线循环的至少一个启动间隔，并激活推测指令。然后执行软件流水线循环的后续启动间隔。

8. 发明授权

US06820250B2 Mechanism for software pipelining loop nests 失效
标题翻译：软件流水线环路机制
公开(公告)号：US06820250B2
公开(公告)日：2004-11-16
申请号：US10143163
申请日：2002-05-09
申请人： Kalyan Muthukumar , Gautam B. Doshi
发明人： Kalyan Muthukumar , Gautam B. Doshi
IPC分类号： G06F944
CPC分类号： G06F8/4452
摘要： A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.
摘要翻译：提供了一种处理嵌套循环的方法，该嵌套循环在外循环中包括模调度内循环。嵌套循环调度为执行外循环的给定迭代的内循环的epilog阶段，其中内循环的前序级用于外循环的下一次迭代。对于本发明的一个实施例，这通过将用于内部循环的epilog计数器初始化为绕过排出软件流水线的值来实现。这会导致处理器在开始耗尽内循环管线之前退出内循环。内循环流水线在外循环的下一次迭代期间排出，而内循环流水线填满外循环的下一次迭代。

9. 发明授权

US06321330B1 Each iteration array selective loop data prefetch in multiple data width prefetch system using rotating register and parameterization to avoid redundant prefetch 有权
标题翻译：每个迭代数组选择循环数据预取在多个数据宽度预取系统中使用旋转寄存器和参数化来避免冗余预取
公开(公告)号：US06321330B1
公开(公告)日：2001-11-20
申请号：US09322196
申请日：1999-05-28
申请人： Gautam B. Doshi , Kalyan Muthukumar
发明人： Gautam B. Doshi , Kalyan Muthukumar
IPC分类号： G06F934
CPC分类号： G06F9/383 , G06F9/30047 , G06F9/30072 , G06F9/30105 , G06F9/30127 , G06F9/3013 , G06F9/325 , G06F9/3455 , G06F9/384
摘要： The present invention provides a mechanism for prefetching array data efficiently from within a loop. A prefetch instruction is parameterized by a register from a set of rotating registers. On each loop iteration, a prefetch is implemented according to the parameterized prefetch instruction, and the address targeted by the prefetch instruction is adjusted. The registers are rotated for each loop iteration, and the prefetch instruction parameterized by the rotating register is adjusted accordingly. The number of iterations between prefetches for a given array is determined by the number of elements in the set of rotating register.
摘要翻译：本发明提供了一种用于从循环内有效地预取数组数据的机制。预取指令由来自一组旋转寄存器的寄存器参数化。在每个循环迭代中，根据参数化的预取指令实现预取，并且调整由预取指令指定的地址。对于每个循环迭代，寄存器被旋转，并且相应地调整由旋转寄存器参数化的预取指令。给定数组的预取之间的迭代次数由旋转寄存器组中的元素数决定。

10. 发明申请

US20120089852A1 ENERGY OPTIMIZATION TECHNIQUES IN A COMPUTING SYSTEM 有权
标题翻译：计算机系统能源优化技术
公开(公告)号：US20120089852A1
公开(公告)日：2012-04-12
申请号：US13018810
申请日：2011-02-01
申请人： Kalyan Muthukumar , Seshadri Harinarayanan , Rama Kishan V. Malladi , Raghavendra S. Hebbalalu , Mukesh Gangadhar
发明人： Kalyan Muthukumar , Seshadri Harinarayanan , Rama Kishan V. Malladi , Raghavendra S. Hebbalalu , Mukesh Gangadhar
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions.
摘要翻译：计算平台可以包括用于确定多个区域中的每一个的性能损失值和能量节省值和/或应用程序内的多个区域中的每一个的存储器有界值的组件。计算平台可以为用户提供用户界面以提供用户输入，其提供可接受的性能损失的指示。为了提供的性能损失值，可以确定频率值，并且可以在处理多个区域中的每个区域的同时以频率值操作处理元件。

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