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1. 发明授权

US06820250B2 Mechanism for software pipelining loop nests 失效
标题翻译：软件流水线环路机制
公开(公告)号：US06820250B2
公开(公告)日：2004-11-16
申请号：US10143163
申请日：2002-05-09
申请人： Kalyan Muthukumar , Gautam B. Doshi
发明人： Kalyan Muthukumar , Gautam B. Doshi
IPC分类号： G06F944
CPC分类号： G06F8/4452
摘要： A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.
摘要翻译：提供了一种处理嵌套循环的方法，该嵌套循环在外循环中包括模调度内循环。嵌套循环调度为执行外循环的给定迭代的内循环的epilog阶段，其中内循环的前序级用于外循环的下一次迭代。对于本发明的一个实施例，这通过将用于内部循环的epilog计数器初始化为绕过排出软件流水线的值来实现。这会导致处理器在开始耗尽内循环管线之前退出内循环。内循环流水线在外循环的下一次迭代期间排出，而内循环流水线填满外循环的下一次迭代。

2. 发明授权

US06321330B1 Each iteration array selective loop data prefetch in multiple data width prefetch system using rotating register and parameterization to avoid redundant prefetch 有权
标题翻译：每个迭代数组选择循环数据预取在多个数据宽度预取系统中使用旋转寄存器和参数化来避免冗余预取
公开(公告)号：US06321330B1
公开(公告)日：2001-11-20
申请号：US09322196
申请日：1999-05-28
申请人： Gautam B. Doshi , Kalyan Muthukumar
发明人： Gautam B. Doshi , Kalyan Muthukumar
IPC分类号： G06F934
CPC分类号： G06F9/383 , G06F9/30047 , G06F9/30072 , G06F9/30105 , G06F9/30127 , G06F9/3013 , G06F9/325 , G06F9/3455 , G06F9/384
摘要： The present invention provides a mechanism for prefetching array data efficiently from within a loop. A prefetch instruction is parameterized by a register from a set of rotating registers. On each loop iteration, a prefetch is implemented according to the parameterized prefetch instruction, and the address targeted by the prefetch instruction is adjusted. The registers are rotated for each loop iteration, and the prefetch instruction parameterized by the rotating register is adjusted accordingly. The number of iterations between prefetches for a given array is determined by the number of elements in the set of rotating register.
摘要翻译：本发明提供了一种用于从循环内有效地预取数组数据的机制。预取指令由来自一组旋转寄存器的寄存器参数化。在每个循环迭代中，根据参数化的预取指令实现预取，并且调整由预取指令指定的地址。对于每个循环迭代，寄存器被旋转，并且相应地调整由旋转寄存器参数化的预取指令。给定数组的预取之间的迭代次数由旋转寄存器组中的元素数决定。

3. 发明申请

US20150268711A1 Selecting A Low Power State Based On Cache Flush Latency Determination 有权
标题翻译：基于缓存冲突延迟确定选择低功耗状态
公开(公告)号：US20150268711A1
公开(公告)日：2015-09-24
申请号：US14221696
申请日：2014-03-21
申请人： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
发明人： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3296 , G06F12/0804 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/128 , G06F2212/1028 , G06F2212/314 , G06F2212/621 , G06F2212/69 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/152 , Y02D10/172 , Y02D50/20
摘要： In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核以独立地执行指令，耦合到核的共享高速缓存并且包括多条线来存储数据，以及包括低功率控制逻辑的功率控制器来计算冲洗等待时间所述共享高速缓存基于所述多条线路的状态。描述和要求保护其他实施例。

4. 发明申请

US20050071607A1 System, method, and apparatus for spilling and filling rotating registers in software-pipelined loops 失效
标题翻译：用于在软件流水线循环中溢出和填充旋转寄存器的系统，方法和装置
公开(公告)号：US20050071607A1
公开(公告)日：2005-03-31
申请号：US10673741
申请日：2003-09-29
申请人： Kalyan Muthukumar
发明人： Kalyan Muthukumar
IPC分类号： G06F9/30 , G06F9/45 , G06F15/00
CPC分类号： G06F9/3013 , G06F8/4452 , G06F9/30134
摘要： An efficient method for software-pipelining (SWP) of loops to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer. In one example embodiment, this is accomplished by spilling and filling multiple computed values, in a register, that are live across multiple stages in a software-pipelined loop, using multiple rotating stack memory locations to reduce compiler-time of SWP, and complexity of the implemented SWP.
摘要翻译：一种循环软件流水线（SWP）的有效方法，用于将程序从较高级别的语言翻译成等效对象或机器语言代码，以便在计算机上执行。在一个示例实施例中，这是通过使用多个旋转堆栈存储器位置溢出并填充在寄存器中的多个计算值来实现的，所述多个计算值在软件流水线循环中的多个阶段处于活动状态，以减少SWP的编译器时间和复杂度实施的SWP。

5. 发明授权

US08843775B2 Energy optimization techniques in a computing system 有权
标题翻译：计算系统中的能量优化技术
公开(公告)号：US08843775B2
公开(公告)日：2014-09-23
申请号：US13018810
申请日：2011-02-01
申请人： Kalyan Muthukumar , Seshadri Harinarayanan , Rama Kishan V. Malladi , Raghavendra S. Hebbalalu , Mukesh Gangadhar
发明人： Kalyan Muthukumar , Seshadri Harinarayanan , Rama Kishan V. Malladi , Raghavendra S. Hebbalalu , Mukesh Gangadhar
IPC分类号： G06F1/26 , G06F1/00 , G06F9/00
CPC分类号： G06F1/3206 , G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions.
摘要翻译：计算平台可以包括用于确定多个区域中的每一个的性能损失值和能量节省值和/或应用程序内的多个区域中的每一个的存储器有界值的组件。计算平台可以为用户提供用户界面以提供用户输入，其提供可接受的性能损失的指示。为了提供的性能损失值，可以确定频率值，并且可以在处理多个区域中的每个区域的同时以频率值操作处理元件。

6. 发明授权

US06912709B2 Mechanism to avoid explicit prologs in software pipelined do-while loops 失效
标题翻译：机制避免在软件流水线的do-while循环中的明确序言
公开(公告)号：US06912709B2
公开(公告)日：2005-06-28
申请号：US09753254
申请日：2000-12-29
申请人： David A Helder , Kalyan Muthukumar
发明人： David A Helder , Kalyan Muthukumar
IPC分类号： G06F9/30 , G06F9/44 , G06F9/48
CPC分类号： G06F9/4881
摘要： The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined loop is initialized with a speculative instruction deactivated. At least one initiation interval of the software-pipelined loop is executed, and the speculative instruction is activated. Subsequent initiation intervals of the software-pipelined loop are then executed.
摘要翻译：本发明提供了一种促进软件流水线循环内的指令执行的机制。根据本发明的一个实施例，软件流水线循环被初始化，推测性指令被禁用。执行软件流水线循环的至少一个启动间隔，并激活推测指令。然后执行软件流水线循环的后续启动间隔。

7. 发明申请

US20120089852A1 ENERGY OPTIMIZATION TECHNIQUES IN A COMPUTING SYSTEM 有权
标题翻译：计算机系统能源优化技术
公开(公告)号：US20120089852A1
公开(公告)日：2012-04-12
申请号：US13018810
申请日：2011-02-01
申请人： Kalyan Muthukumar , Seshadri Harinarayanan , Rama Kishan V. Malladi , Raghavendra S. Hebbalalu , Mukesh Gangadhar
发明人： Kalyan Muthukumar , Seshadri Harinarayanan , Rama Kishan V. Malladi , Raghavendra S. Hebbalalu , Mukesh Gangadhar
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions.
摘要翻译：计算平台可以包括用于确定多个区域中的每一个的性能损失值和能量节省值和/或应用程序内的多个区域中的每一个的存储器有界值的组件。计算平台可以为用户提供用户界面以提供用户输入，其提供可接受的性能损失的指示。为了提供的性能损失值，可以确定频率值，并且可以在处理多个区域中的每个区域的同时以频率值操作处理元件。

8. 发明申请

US20100077145A1 METHOD AND SYSTEM FOR PARALLEL EXECUTION OF MEMORY INSTRUCTIONS IN AN IN-ORDER PROCESSOR 审中-公开
标题翻译：在订单处理器中并行执行存储器指令的方法和系统
公开(公告)号：US20100077145A1
公开(公告)日：2010-03-25
申请号：US12238341
申请日：2008-09-25
申请人： Sebastian C. Winkel , Kalyan Muthukumar , Don C. Soltis, JR.
发明人： Sebastian C. Winkel , Kalyan Muthukumar , Don C. Soltis, JR.
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/3861 , G06F12/0859
摘要： A method of parallel execution of a first and a second instruction in an in-order processor. Embodiments of the invention enable parallel execution of memory instructions that are stalled by cache memory misses. The in-order processor processes cache memory misses of instructions in parallel by overlapping the first cache memory miss with cache memory misses that occur after the first cache memory miss. Memory-level parallelism in the in-order processor can be increased when more parallel and outstanding cache memory misses are generated.
摘要翻译：一种在顺序处理器中并行执行第一和第二指令的方法。本发明的实施例使得能够并行执行由高速缓存存储器未命中停滞的存储器指令。按顺序处理器通过将第一高速缓存存储器未命中与在第一高速缓冲存储器未命中之后发生的高速缓存存储器未命中重叠来并行处理高速缓存存储器未命中。当产生更多并行和未完成的高速缓存存储器未命中时，可以增加按顺序处理器中的存储器级并行性。

9. 发明申请

US20070079302A1 Method for predicate promotion in a software loop 失效
标题翻译：软件循环中谓词升级的方法
公开(公告)号：US20070079302A1
公开(公告)日：2007-04-05
申请号：US11241144
申请日：2005-09-30
申请人： Kalyan Muthukumar , Robyn Sampson , Daniel Lavery
发明人： Kalyan Muthukumar , Robyn Sampson , Daniel Lavery
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/433
摘要： A method and system for optimizing the execution of a software loop is provided. The method involves the determination of an edge in a critical recurrence cycle in the software loop. The edge is a dependency link between two instructions and contains a dependee and a dependent. The dependee is an instruction that produces a result, and the dependent is an instruction that uses the result. The method further involves performing predicate promotion of at least one of the dependee and the dependent if one or more pre-determined conditions are met.
摘要翻译：提供了一种用于优化软件循环执行的方法和系统。该方法涉及在软件循环中确定临界循环中的边缘。边缘是两条指令之间的依赖关系，包含一个依赖关系和一个依赖关系。依赖者是产生结果的指令，依赖关系是使用结果的指令。该方法还涉及如果满足一个或多个预定条件，则执行至少一个依赖者和依赖者的谓词升级。

10. 发明授权

US06839895B1 Method of, system for, and computer program product for providing efficient utilization of memory hierarchy through code restructuring 有权
标题翻译：方法，系统和计算机程序产品，通过代码重组提供有效利用存储器层次结构
公开(公告)号：US06839895B1
公开(公告)日：2005-01-04
申请号：US09685481
申请日：2000-10-10
申请人： Dz Ching Ju , Kalyan Muthukumar , Shankar Ramaswamy , Barbara Bluestein Simons
发明人： Dz Ching Ju , Kalyan Muthukumar , Shankar Ramaswamy , Barbara Bluestein Simons
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Code restructuring or reordering based on profiling information and memory hierarchy is provided by constructing a Program Execution Graph (PEG) corresponding to a level of the memory hierarchy, partitioning this PEG to reduce estimated memory overhead costs below an upper bound, and constructing a PEG for a next level of the memory hierarchy from the partitioned PEG. The PEG is constructed from control flow and frequency information from a profile of the program to be restructured. The PEG is a weighted undirected graph comprising nodes representing basic blocks and edges representing transfer of control between pairs of basic blocks. The weight of a node is the size of the basic block it represents and the weight of an edge is the frequency of transition between the pair of basic blocs it connects.
摘要翻译：通过构建对应于存储器层级的级别的程序执行图（PEG）来提供基于分析信息和存储器层次结构的代码重构或重新排序，对该PEG进行划分以减少低于上限的估计的内存开销成本，以及构建用于来自分区PEG的内存层次结构的下一级别。 PEG由要重组程序的配置文件的控制流程和频率信息构成。 PEG是加权无向图，包括表示基本块的节点和表示基本块对之间的控制传输的边。节点的权重是其表示的基本块的大小，边的权重是其连接的一对基本块之间的转换频率。

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