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1. 发明授权

US06597690B1 Method and apparatus employing associative memories to implement limited switching 失效
标题翻译：使用关联存储器实现有限切换的方法和装置
公开(公告)号：US06597690B1
公开(公告)日：2003-07-22
申请号：US09235197
申请日：1999-01-22
申请人： Kalpesh D. Mehta , Krishna Shetty
发明人： Kalpesh D. Mehta , Krishna Shetty
IPC分类号： H04Q1104
CPC分类号： H04Q11/04 , H04Q2213/13103
摘要： A method for employing an associative memory to implement a switch is disclosed. The method comprises the step of receiving data in a first time slot. The method also comprises the step of examining the associative memory to determine if the data should be stored. Additionally, the method comprises the step of storing the data in a memory location and transmitting the data in a second time slot.
摘要翻译：公开了一种采用联想存储器实现开关的方法。该方法包括在第一时隙中接收数据的步骤。该方法还包括检查关联存储器以确定是否应该存储数据的步骤。此外，该方法包括将数据存储在存储器位置中并在第二时隙中发送数据的步骤。

2. 发明授权

US06570887B2 Method and apparatus employing associative memories to implement message passing 失效
标题翻译：使用关联存储器来实现消息传递的方法和装置
公开(公告)号：US06570887B2
公开(公告)日：2003-05-27
申请号：US09235867
申请日：1999-01-22
申请人： Kalpesh D. Mehta , Krishna Shetty
发明人： Kalpesh D. Mehta , Krishna Shetty
IPC分类号： H04B7212
CPC分类号： G06F13/387
摘要： A method for employing an associative memory to implement a message passing switch. The method comprising the step of receiving data in a time slot. The method also comprising the step of examining an interrupt register to determine if the data is a message. Additionally, the method comprises the step of storing the data in a memory location and transferring the data to an external device.
摘要翻译：一种使用关联存储器来实现消息传递交换机的方法。该方法包括在时隙中接收数据的步骤。该方法还包括检查中断寄存器以确定数据是否是消息的步骤。此外，该方法包括将数据存储在存储器位置并将数据传送到外部设备的步骤。

3. 发明授权

US07114023B2 Non-sequential access pattern based address generator 失效
标题翻译：基于非顺序访问模式的地址生成器
公开(公告)号：US07114023B2
公开(公告)日：2006-09-26
申请号：US10651379
申请日：2003-08-29
申请人： Wen-Shan Wang , Kalpesh D. Mehta
发明人： Wen-Shan Wang , Kalpesh D. Mehta
IPC分类号： G11C8/04
CPC分类号： G06F9/345 , G06F9/3552 , G11C8/04 , G11C2029/3602
摘要： An address generator is provided with an input to receive a base address for an array of storage locations, an offset generator to generate a number of offsets, and a combiner coupled to the input and the offset generator to combine the base address with the offsets to generate a number of access addresses for accessing the array of storage locations in accordance with a deterministic access pattern having at least one non-sequential access. In various embodiments, the address generator is included in each of a number of signal processing units, which in turn are included in a digital media processor.
摘要翻译：地址发生器具有输入以接收存储位置阵列的基址，产生多个偏移的偏移发生器，以及耦合到输入端和偏移发生器的组合器，以将基址与偏移组合到根据具有至少一个非顺序访问的确定性访问模式，生成用于访问存储位置阵列的多个访问地址。在各种实施例中，地址发生器被包括在多个信号处理单元中的每一个中，其又被包括在数字媒体处理器中。

4. 发明授权

US08705632B2 Decoder architecture systems, apparatus and methods 有权
标题翻译：解码器架构系统，设备和方法
公开(公告)号：US08705632B2
公开(公告)日：2014-04-22
申请号：US11093732
申请日：2005-03-30
申请人： Eric F. Vannerson , Kalpesh D. Mehta , Louis A. Lippincott
发明人： Eric F. Vannerson , Kalpesh D. Mehta , Louis A. Lippincott
IPC分类号： H04N7/12
CPC分类号： H04N19/625 , H04N19/12 , H04N19/42 , H04N19/44 , H04N19/70 , H04N19/91
摘要： An apparatus includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.
摘要翻译：一种装置包括：解码器，用于接收基于编码标准的压缩比特流。解码器包括硬件加速器，用于对基于包括编码标准的多个编码标准中通用的操作的压缩比特流的一部分进行解码。解码器还包括可编程元件，用于对基于编码标准特有的操作的压缩比特流的一部分进行解码。

5. 发明授权

US07864864B2 Context buffer address determination using a plurality of modular indexes 有权
标题翻译：使用多个模块化索引确定上下文缓冲区地址
公开(公告)号：US07864864B2
公开(公告)日：2011-01-04
申请号：US11168896
申请日：2005-06-27
申请人： Kalpesh D. Mehta , Wen-Shan Wang
发明人： Kalpesh D. Mehta , Wen-Shan Wang
IPC分类号： H04N7/12 , H04B1/66
CPC分类号： H04N19/176 , H04N19/423 , H04N19/593
摘要： According to some embodiments, context information is accessed for a current image block being processed. The context information may be, for example, associated with a block neighboring the current block, and the accessing may be performed in accordance with an address. At least one of a plurality of modular indexes may then be adjusted, and a next address may be determined in accordance with the plurality of modular indexes.
摘要翻译：根据一些实施例，对正在处理的当前图像块访问上下文信息。上下文信息可以例如与与当前块相邻的块相关联，并且可以根据地址来执行访问。然后可以调整多个模块化索引中的至少一个，并且可以根据多个模块索引来确定下一个地址。

6. 发明授权

US07590300B2 Image filtering methods and apparatus 有权
标题翻译：图像滤波方法及装置
公开(公告)号：US07590300B2
公开(公告)日：2009-09-15
申请号：US10876235
申请日：2004-06-24
申请人： Shashikiran H. Tadas , Kalpesh D. Mehta
发明人： Shashikiran H. Tadas , Kalpesh D. Mehta
IPC分类号： G06K9/40
CPC分类号： G06T5/20
摘要： In one embodiment, a method and apparatus for filtering input pixel data is configurable to perform a one-dimensional or two-dimensional filtering process. Further, in one embodiment, the two-dimensional filter can be configured to perform a separable or non-separable filter. The type of filter can be configured, along with the size of the filter and other parameters. During operation, a stage I filtering operation performs a portion of the filter, and temporarily stores the result in a storage element. If the filter is a one-dimensional filter, then the results are sent to be post-processed. If the filter is a two-dimensional filter, then a stage II filtering process is performed or the intermediate results are added together, based on whether the filter is separable or non-separable. These results are then post-processed.
摘要翻译：在一个实施例中，用于滤波输入像素数据的方法和装置可配置为执行一维或二维滤波处理。此外，在一个实施例中，二维滤波器可以被配置为执行可分离或不可分离的滤波器。可以配置过滤器的类型，以及过滤器的尺寸和其他参数。在操作期间，阶段I过滤操作执行过滤器的一部分，并将结果临时存储在存储元件中。如果过滤器是一维过滤器，则将结果发送到后处理。如果滤波器是二维滤波器，则基于滤波器是否可分离或不可分离，执行阶段II滤波处理或将中间结果相加在一起。然后对这些结果进行后处理。

7. 发明授权

US07130986B2 Determining if a register is ready to exchange data with a processing element 有权
标题翻译：确定寄存器是否准备好与处理元件交换数据
公开(公告)号：US07130986B2
公开(公告)日：2006-10-31
申请号：US10609706
申请日：2003-06-30
申请人： Kalpesh D. Mehta , Louis A. Lippincott , Eric F. Vannerson
发明人： Kalpesh D. Mehta , Louis A. Lippincott , Eric F. Vannerson
IPC分类号： G06F15/82
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3838
摘要： According to some embodiments, it is determined if a register is ready to exchange data with a processing element.
摘要翻译：根据一些实施例，确定寄存器是否准备好与处理元件交换数据。

8. 发明授权

US07496921B2 Processing block with integrated light weight multi-threading support 有权
标题翻译：加工块具有集成轻便多线程支持
公开(公告)号：US07496921B2
公开(公告)日：2009-02-24
申请号：US10651381
申请日：2003-08-29
申请人： Kalpesh D. Mehta
发明人： Kalpesh D. Mehta
IPC分类号： G06F9/46 , G06F9/40 , G06F9/44
CPC分类号： G06F9/3009 , G06F9/3851 , G06F9/485
摘要： A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various embodiments, the structure includes a current thread identifier, and a thread array of thread entries describing the threads to be executed interleavingly. Further, in various embodiments, the processing block includes an execution sub-block and a thread management sub-block equipped to support at least a create thread, a thread execution termination, and a thread execution switching instruction.
摘要翻译：处理块配有存储器，以便于线切换结构的存储和维护，以轻量化的方式提供多线程支持。在各种实施例中，该结构包括当前线程标识符和描述要交错执行的线程的线程条目的线程数组。此外，在各种实施例中，处理块包括执行子块和配置为至少支持创建线程，线程执行终止和线程执行切换指令的线程管理子块。

9. 发明授权

US07457363B2 Method and apparatus for multi-threaded variable length coding 有权
标题翻译：用于多线程可变长度编码的方法和装置
公开(公告)号：US07457363B2
公开(公告)日：2008-11-25
申请号：US10882973
申请日：2004-06-30
申请人： Suketu R. Partiwala , Kalpesh D. Mehta
发明人： Suketu R. Partiwala , Kalpesh D. Mehta
IPC分类号： H04B1/66
CPC分类号： H03M7/425 , H04N19/42 , H04N19/91
摘要： A device including a variable length coding unit that includes an input unit connected to a stream switching unit, and an output unit connected to the stream switching unit. The input unit to encode at least two input streams simultaneously. The output unit to transmit output streams to an output interface connected to the output unit.
摘要翻译：一种包括可变长度编码单元的装置，包括连接到流切换单元的输入单元和连接到流切换单元的输出单元。所述输入单元同时对至少两个输入流进行编码。输出单元将输出流传输到连接到输出单元的输出接口。

10. 发明授权

US07113115B2 Variable length code table look ups 有权
公开(公告)号：US07113115B2
公开(公告)日：2006-09-26
申请号：US10882460
申请日：2004-06-30
申请人： Suketu R. Partiwala , Kalpesh D. Mehta
发明人： Suketu R. Partiwala , Kalpesh D. Mehta
IPC分类号： H03M7/40
CPC分类号： H03M7/42 , H04N19/42 , H04N19/60 , H04N19/61 , H04N19/91
摘要： Embodiments relate to converting or compressing symbols or run, level pair of an input digital video or image data stream to variable length code (VLC) by looking the symbols or run, level pairs up in a table including a binary code, a length code, and a flip code and constructing the VLC therefrom. For instance, the binary code may identify a first non-zero portion of the VLC, the length may identify the length of the VLC, and the flip code may identify whether or not the first portion and a number of 0's appended to the first portion to form a VLC having the length given by the length code, must be inverted to create the VLC. Also, the table may include entries grouped according to symbol or run, level pair values, and an address offset determined by the symbol or run, level pair or the input may be used to access the binary, length, and flip code from the appropriate group.

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