专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6092142A Method and apparatus to introduce programmable delays when replaying isochronous data packets 失效
标题翻译：在重放等时数据包时引入可编程延迟的方法和装置
公开(公告)号：US6092142A
公开(公告)日：2000-07-18
申请号：US31390
申请日：1998-02-26
申请人： Kalpesh Mehta , Krishna Shetty , Sailesh Bissessur , Seng Thien Yap
发明人： Kalpesh Mehta , Krishna Shetty , Sailesh Bissessur , Seng Thien Yap
IPC分类号： H04L12/40 , H04L12/64 , G06F13/00
CPC分类号： H04L12/40052 , H04L12/6418
摘要： A method and apparatus for introducing a programmable delay during replay of isochronous data packets is described. The method includes, determining an initial delay point. In particular, the initial delay point is determined by the transmission rate, playback rate, and the desired buffer storage size. The method also includes, introducing a programmable delay to synchronize playback of multiple data streams across multiple destination devices. The apparatus includes, a buffer, a switching device, a counter, and control logic to insert the programmable delay.
摘要翻译：描述了在同步数据分组的重放期间引入可编程延迟的方法和装置。该方法包括确定初始延迟点。特别地，初始延迟点由传输速率，播放速率和期望的缓冲存储器大小确定。该方法还包括引入可编程延迟以跨多个目的地设备同步多个数据流的重放。该装置包括缓冲器，开关装置，计数器和用于插入可编程延迟的控制逻辑。

2. 发明授权

US5884102A Method and apparatus for a configurable means of connection between an embedded processor and a personal computer 失效
标题翻译：用于嵌入式处理器和个人计算机之间可配置连接装置的方法和装置
公开(公告)号：US5884102A
公开(公告)日：1999-03-16
申请号：US865801
申请日：1997-05-30
申请人： David George England , Krishna Shetty
发明人： David George England , Krishna Shetty
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4068
摘要： The invention provides an enhanced peripheral device that can connect to a computer in either in one of two modes: A PCMCIA mode and a serial mode. This allows the device to continue communicating with computer even if unplugged from the PCMCIA connector. Detection circuitry is used to determine whether the peripheral device is connected using the PCMCIA connector or the serial connector. Switching circuitry then routes data from connected connector to the various data handing units, such as UARTs present in the peripheral and the computer.
摘要翻译：本发明提供了一种增强的外围设备，其可以以两种模式之一连接到计算机：PCMCIA模式和串行模式。这样即使从PCMCIA连接器拔出也可以使设备继续与计算机进行通信。检测电路用于确定外围设备是否使用PCMCIA连接器或串行连接器进行连接。然后，交换电路将数据从连接的连接器路由到各种数据处理单元，例如外围设备和计算机中存在的UART。

3. 发明授权

US06597690B1 Method and apparatus employing associative memories to implement limited switching 失效
标题翻译：使用关联存储器实现有限切换的方法和装置
公开(公告)号：US06597690B1
公开(公告)日：2003-07-22
申请号：US09235197
申请日：1999-01-22
申请人： Kalpesh D. Mehta , Krishna Shetty
发明人： Kalpesh D. Mehta , Krishna Shetty
IPC分类号： H04Q1104
CPC分类号： H04Q11/04 , H04Q2213/13103
摘要： A method for employing an associative memory to implement a switch is disclosed. The method comprises the step of receiving data in a first time slot. The method also comprises the step of examining the associative memory to determine if the data should be stored. Additionally, the method comprises the step of storing the data in a memory location and transmitting the data in a second time slot.
摘要翻译：公开了一种采用联想存储器实现开关的方法。该方法包括在第一时隙中接收数据的步骤。该方法还包括检查关联存储器以确定是否应该存储数据的步骤。此外，该方法包括将数据存储在存储器位置中并在第二时隙中发送数据的步骤。

4. 发明授权

US06570887B2 Method and apparatus employing associative memories to implement message passing 失效
标题翻译：使用关联存储器来实现消息传递的方法和装置
公开(公告)号：US06570887B2
公开(公告)日：2003-05-27
申请号：US09235867
申请日：1999-01-22
申请人： Kalpesh D. Mehta , Krishna Shetty
发明人： Kalpesh D. Mehta , Krishna Shetty
IPC分类号： H04B7212
CPC分类号： G06F13/387
摘要： A method for employing an associative memory to implement a message passing switch. The method comprising the step of receiving data in a time slot. The method also comprising the step of examining an interrupt register to determine if the data is a message. Additionally, the method comprises the step of storing the data in a memory location and transferring the data to an external device.
摘要翻译：一种使用关联存储器来实现消息传递交换机的方法。该方法包括在时隙中接收数据的步骤。该方法还包括检查中断寄存器以确定数据是否是消息的步骤。此外，该方法包括将数据存储在存储器位置并将数据传送到外部设备的步骤。

5. 发明授权

US5602884A Digital phase locked loop 失效
标题翻译：数字锁相环
公开(公告)号：US5602884A
公开(公告)日：1997-02-11
申请号：US440939
申请日：1995-05-15
申请人： Jerzy Wieczorkiewicz , Krishna Shetty , Terry Kenny , Robert L. van der Valk , Menno T. Spijker
发明人： Jerzy Wieczorkiewicz , Krishna Shetty , Terry Kenny , Robert L. van der Valk , Menno T. Spijker
IPC分类号： H03L7/081 , H03D3/24
CPC分类号： H03L7/081
摘要： A digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop included a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in the output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.
摘要翻译：公开了用于从至少一个受抖动的输入信号恢复稳定时钟信号的数字锁相环。该回路包括接收至少一个输入信号的数字输入电路，用于产生期望频率的输出信号的数字控制振荡器和表示输出信号中的时间误差的控制信号，稳定的本地振荡器，用于向数字控制振荡器和用于接收数字控制振荡器的输出信号的抽头延迟线。抽头延迟线包括多个缓冲器，每个缓冲器引入小于数字控制振荡器的一个时钟周期的延迟。抽头延迟线从由控制信号确定的抽头产生输出信号。数字相位比较器从输入电路接收至少一个输入信号和来自抽头延迟线的输出信号，以产生控制数字控制振荡器的数字输入信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式