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1. 发明授权

US6156602A Self-aligned precise high sheet RHO register for mixed-signal application 失效
标题翻译：自对准精密高片材RHO电阻，用于混合信号应用
公开(公告)号：US6156602A
公开(公告)日：2000-12-05
申请号：US368859
申请日：1999-08-06
申请人： Kai Shao , Shao-Fu Sanford Chu , Cerdin Lee
发明人： Kai Shao , Shao-Fu Sanford Chu , Cerdin Lee
IPC分类号： H01L21/02 , H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L28/56
摘要： A new method is provided for the creation of a resistive load in a semiconductor device whereby the semiconductor device further contains gate electrodes and a capacitor. Field isolation regions separate the active areas; a thin layer of gate oxide is created over these active regions. A first layer of poly is deposited, used for the gate electrode, for the bottom plate of the adjacent capacitor and for the resistor of high ohmic value. The gate poly is doped (in the first layer of poly); optionally the bottom plate of the capacitor can be doped. A dielectric layer is deposited for the dielectric of the capacitor; a second layer of poly is deposited, patterned and etched to form the capacitor top plate. The capacitor (dielectric and bottom plate), poly gates and the load resistor are patterned; the LDD regions for the transistors are created. The (gate, capacitor, resistor) spacers are formed, during and as part of the etch of the gate spacers a resistive spacer (called spacer since it serves to space or separate the two contact points of the resistor) is formed. The source/drain implants for the gate electrodes are performed thereby concurrently performing (self-aligned, due to the resistor spacer) implants for the contact regions of the resistor. All contacts (gate poly, source/drain and two contact points on the resistor) are salicided to achieve lower contact resistance.
摘要翻译：提供了一种用于在半导体器件中产生电阻性负载的新方法，由此半导体器件还包含栅电极和电容器。现场隔离区分开活动区域; 在这些活性区域上形成薄层的栅极氧化物。沉积第一层poly，用于栅电极，用于相邻电容器的底板和高欧姆值的电阻。掺杂多晶硅（在第一层聚合物中）; 可选地，可以掺杂电容器的底板。为电容器的电介质沉积电介质层; 沉积第二层多晶硅，进行图案化和蚀刻以形成电容器顶板。电容器（电介质和底板），多晶硅栅极和负载电阻器被图案化; 产生晶体管的LDD区域。形成（栅极，电容器，电阻器）间隔物，在蚀刻栅极隔离物期间和作为蚀刻的一部分期间，形成电阻隔离物（称为间隔物，因为其用于空间或分离电阻器的两个接触点）。执行栅电极的源极/漏极注入，由此同时对电阻器的接触区域进行（由于电阻器隔离物而自对准）植入物。所有触点（栅极多晶硅，源极/漏极和电阻上的两个接触点）都被浸渍以实现较低的接触电阻。

2. 发明授权

US6159759A Method to form liquid crystal displays using a triple damascene technique 有权
标题翻译：使用三重镶嵌技术形成液晶显示器的方法
公开(公告)号：US6159759A
公开(公告)日：2000-12-12
申请号：US443423
申请日：1999-11-19
申请人： Kai Shao , Cerdin Lee , Yi Xu , Shao-Fu Sanford Chu
发明人： Kai Shao , Cerdin Lee , Yi Xu , Shao-Fu Sanford Chu
IPC分类号： G02F1/1335 , G02F1/1362 , H01L21/00
CPC分类号： G02F1/133553 , G02F1/136277
摘要： A new method of forming liquid crystal displays has been achieved. Metal conductors are provided in an insulating layer overlying a semiconductor substrate. A first isolation layer is deposited. A first silicon nitride layer is deposited. The first silicon nitride layer is patterned to form openings for planned vias overlying the metal conductors. A second isolation layer is deposited. A second silicon nitride layer is deposited. The second silicon nitride layer is patterned to form masks overlying where dummy supports for the metal pixels are planned and to form openings to extend the planned vias. A third isolation layer is deposited. The third isolation layer is patterned to form openings for the planned metal pixels. The second isolation layer and the first isolation layer are etched through to complete the vias and the dummy supports. A metal layer is deposited filling the openings for the metal pixels, the dummy support, and the vias. The metal layer is polished down to the top surface of the third isolation layer to complete the metal pixels. A thin film passivation is deposited. A liquid crystal layer is deposited. A transparent image point electrode is formed to complete the liquid crystal display.
摘要翻译：已经实现了一种形成液晶显示器的新方法。金属导体设置在覆盖半导体衬底的绝缘层中。沉积第一隔离层。沉积第一氮化硅层。图案化第一氮化硅层以形成覆盖金属导体的计划通孔的开口。沉积第二隔离层。沉积第二氮化硅层。图案化第二氮化硅层以形成掩模，覆盖着金属像素的虚拟支撑被设计并形成扩展计划的通孔的开口。沉积第三个隔离层。图案化第三隔离层以形成用于计划的金属像素的开口。蚀刻第二隔离层和第一隔离层以完成通孔和虚拟支撑。沉积金属层，填充用于金属像素，虚拟支撑件和通孔的开口。金属层被抛光到第三隔离层的顶表面以完成金属像素。沉积薄膜钝化。沉积液晶层。形成透明图像点电极以完成液晶显示器。

3. 发明授权

US6117747A Integration of MOM capacitor into dual damascene process 有权
标题翻译：将MOM电容器集成到双镶嵌工艺中
公开(公告)号：US6117747A
公开(公告)日：2000-09-12
申请号：US435436
申请日：1999-11-22
申请人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
发明人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/20
CPC分类号： H01L28/40 , H01L21/76838 , H01L28/60
摘要： A method for fabricating a metal-oxide-metal capacitor using a dual damascene process is described. A dielectric layer is provided overlying a semiconductor substrate. A dual damascene opening in the dielectric layer is filled with copper to form a copper via underlying a copper line. A first metal layer is deposited overlying the copper line and patterned to form a bottom capacitor plate contacting the copper line. A capacitor dielectric layer is deposited overlying the bottom capacitor plate. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top capacitor plate to complete fabrication of a metal-oxide-metal capacitor.
摘要翻译：描述了使用双镶嵌工艺制造金属氧化物 - 金属电容器的方法。提供覆盖在半导体衬底上的电介质层。电介质层中的双镶嵌开口填充有铜，通过铜线下方形成铜。沉积在铜线上的第一金属层被图案化以形成接触铜线的底部电容器板。电容器电介质层沉积在底部电容器板上。将第二金属层沉积在电容器介电层上并被图案化以形成顶部电容器板，以完成金属氧化物 - 金属电容器的制造。

4. 发明授权

US6124194A Method of fabrication of anti-fuse integrated with dual damascene process 有权
标题翻译：与双镶嵌工艺集成的抗熔丝的制造方法
公开(公告)号：US6124194A
公开(公告)日：2000-09-26
申请号：US439365
申请日：1999-11-15
申请人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
发明人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
IPC分类号： H01L21/768 , H01L23/525 , H07L29/00
CPC分类号： H01L21/7681 , H01L23/5252 , H01L2924/0002
摘要： A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via. Simultaneously, an anti-fuse metal line is formed over the fusing element to form an anti-fuse module within the anti-fuse area, and a dual damascene interconnect is formed over, and contacting with, the second metal line and within the interconnect area.
摘要翻译：一种制造抗熔丝模块和双镶嵌互连结构的方法包括以下步骤。提供具有被第一介电层覆盖的至少两个暴露的金属线的半导体结构。第一金属线在反熔丝区内，第二金属线在互连区内。第一金属通孔形成在反熔丝区域内的第一电介质层内，第一金属通孔接触第一金属线。在第一介电层和第一金属通孔上沉积SiN层。图案化SiN层以形成至少两个开口。第一开口暴露第一金属通孔，第二开口暴露第二电介质层的第二金属线上方的一部分。在图案化的SiN层状结构上沉积并图案化定影元件层，以在第一金属通孔之上形成定影元件。同时，在熔断元件上方形成抗熔丝金属线，以在反熔丝区域内形成反熔丝模块，并且在第二金属线之间和互连区内形成双面镶嵌互连。

5. 发明授权

US06489191B2 Method for forming self-aligned channel implants using a gate poly reverse mask 失效
标题翻译：使用栅极多反向掩模形成自对准沟道植入物的方法
公开(公告)号：US06489191B2
公开(公告)日：2002-12-03
申请号：US10140571
申请日：2002-05-08
申请人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
发明人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , Y10S977/712
摘要： A method for forming a CMOS transistor gate with a self-aligned. channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshhold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
摘要翻译：一种用于形成具有自对准的CMOS晶体管栅极的方法。通道植入。提供具有第一有源区的半导体结构。在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。形成暴露第一通道植入物开口的第一通道植入物掩模。通过第一通道植入物开口注入杂质离子以形成第一阈值调整区域和第一抗穿透区域。在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

6. 发明授权

US6133079A Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions 失效
标题翻译：通过反向P / N结减少薄膜电感器的衬底电容耦合的方法
公开(公告)号：US6133079A
公开(公告)日：2000-10-17
申请号：US358985
申请日：1999-07-22
申请人： Min Zhu , Kai Shao , Shao-Fu Sanford Chu
发明人： Min Zhu , Kai Shao , Shao-Fu Sanford Chu
IPC分类号： H01L21/02 , H01L23/522 , H01L27/06 , H01L27/08 , H01L21/8238
CPC分类号： H01L28/10 , H01L23/5227 , H01L27/0688 , H01L27/08 , H01L2924/0002
摘要： A method for reducing the capacitive coupling of an inductor on an integrated circuit chip is described. The method forms the inductor over an accumulation of dielectric layers used elsewhere in the integrated circuit. In addition two back-to-back reversed p/n junctions are formed within the silicon substrate below the inductor. The junctions are serially connected and, along with the capacitance of the dielectric layers, reduce the capacitive coupling of the inductor to the substrate by a factor of between about 2 and 20 over the that of the dielectric layers alone. The decrease in capacitance improves the performance of the inductor at high operating frequencies, for example, above1 GHz. The junctions are easily formed in a twin-well CMOS circuit by the addition of only a single additional processing step. The additional step comprises the deep implantation of phosphorous to form an n-type zone between the p-well and the substrate in the region over which the inductor is formed. The junctions are not externally biased and sustain continuous depletion regions between the inductor and the substrate.
摘要翻译：描述了用于减小集成电路芯片上的电感器的电容耦合的方法。该方法在集成电路中的其他地方使用的介电层的积累形成电感器。此外，在电感器下面的硅衬底内形成两个背靠背的反向p / n结。接头串联连接，并且与电介质层的电容一起，使电感器与衬底的电容耦合比单独的电介质层的耦合减小约2至20倍。电容的减小改善了高工作频率下电感器的性能，例如高于1GHz。通过添加仅一个附加的处理步骤，可以在双阱CMOS电路中容易地形成结。附加步骤包括在形成电感器的区域中深度注入磷以在p阱和衬底之间形成n型区。接点不是外部偏置的，并且在电感器和衬底之间维持连续的耗尽区。

7. 发明授权

US06410394B1 Method for forming self-aligned channel implants using a gate poly reverse mask 失效
标题翻译：使用栅极多反向掩模形成自对准沟道植入物的方法
公开(公告)号：US06410394B1
公开(公告)日：2002-06-25
申请号：US09465305
申请日：1999-12-17
申请人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
发明人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
IPC分类号： H01L21336
CPC分类号： H01L21/823807 , Y10S977/712
摘要： A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
摘要翻译：一种用于形成具有自对准沟道植入物的CMOS晶体管栅极的方法。提供具有第一有源区的半导体结构。在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。形成暴露第一通道植入物开口的第一通道植入物掩模。杂质离子通过第一通道注入开口注入，以形成第一阈值调整区域和第一抗穿通区域。在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

8. 发明授权

US06291307B1 Method and structure to make planar analog capacitor on the top of a STI structure 失效
标题翻译：在STI结构顶部制作平面模拟电容的方法和结构
公开(公告)号：US06291307B1
公开(公告)日：2001-09-18
申请号：US09368863
申请日：1999-08-06
申请人： Shao-Fu Sanford Chu , Yang Pan , Wang Yimin , Kai Shao
发明人： Shao-Fu Sanford Chu , Yang Pan , Wang Yimin , Kai Shao
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/76224 , H01L27/0629
摘要： A new method is provided to create a capacitor over the surface of STI regions. The STI regions are first created in the surface of the substrate, a layer of sacrificial oxide is next blanket deposited over the substrate (thereby including the surface of the created STI regions). A depletion stop region overlying densely spaced STI regions is formed in the surface of the substrate by N+ ion implantation, N-well and P-well regions are formed surrounding the depletion stop region. An insulation layer is deposited. The sacrificial oxide and insulation layers are patterned and etched leaving the sacrificial oxide and the insulation layer in place where the capacitor is to be created. A layer of gate oxide is formed over the surface of the substrate, a layer of poly 2 is deposited for the bottom plate and the gate electrode. The conductivity of the gate electrode and the bottom plate of the capacitor is established by performing a selective N+ implant into the layer of poly 2 where the gate electrode and the bottom plate of the capacitor are to be formed. A layer of dielectric is deposited for the capacitor dielectric, a layer of in-situ doped poly 3 is deposited for the top plate of the capacitor. The layers of poly 3, dielectric and poly 2 are etched forming the capacitor structure and the gate electrode structure.
摘要翻译：提供了一种新的方法来在STI区域的表面上形成电容器。首先在衬底的表面中形成STI区，然后在衬底上沉积一层牺牲氧化物（从而包括所产生的STI区的表面）。通过N +离子注入在衬底的表面中形成覆盖密集间隔的STI区的耗尽阻挡区，在耗尽阻挡区周围形成N阱和P阱区。沉积绝缘层。牺牲氧化物和绝缘层被图案化和蚀刻，留下牺牲氧化物和绝缘层到位于要产生电容器的位置。在衬底的表面上形成栅极氧化层，为了沉积底层和栅电极，淀积一层聚二氧化硅。通过对形成电容器的栅电极和底板的poly 2层进行选择性N +注入来建立电容器的栅电极和底板的导电性。为电容器电介质沉积一层电介质，为电容器的顶板沉积一层原位掺杂的poly 3。蚀刻形成电容器结构和栅极电极结构的聚3，电介质和聚合物2的层。

9. 发明授权

US06284594B1 Formation of an interpoly capacitor structure using a chemical mechanical polishing procedure 失效
标题翻译：使用化学机械抛光程序形成多层电容器结构
公开(公告)号：US06284594B1
公开(公告)日：2001-09-04
申请号：US09580607
申请日：2000-05-30
申请人： Yong Ju , Kai Shao , Yimin Wang , Shao-Fu Sanford Chu
发明人： Yong Ju , Kai Shao , Yimin Wang , Shao-Fu Sanford Chu
IPC分类号： H01L218242
CPC分类号： H01L27/0629 , H01L21/3144 , H01L28/40
摘要： A process for simultaneously forming a polysilicon gate structure, for a transfer gate transistor, and a polysilicon top plate, for a capacitor structure, on an underlying planar surface, has been developed. The process features the formation of a polysilicon bottom plate, for the capacitor structure, embedded in a first opening in composite insulator layer, and the formation of an active device region, for a transfer gate transistor structure, via the selective growth of an epitaxial silicon layer, in a second opening of the composite insulator layer, resulting in a planar top surface topography. The presence of this topography reduces the risk of residual polysilicon, present after patterning of the polysilicon gate structure, and of the capacitor, polysilicon top plate.
摘要翻译：已经开发了用于在底层平面上形成用于电容器结构的传输栅极晶体管和多晶硅顶板的多晶硅栅极结构的工艺。该方法的特征在于形成多晶硅底板，用于电容器结构，嵌入在复合绝缘体层中的第一开口中，并且通过外延硅的选择性生长形成用于传输栅晶体管结构的有源器件区层，在复合绝缘体层的第二开口中，产生平坦的顶表面形貌。这种形貌的存在降低了在多晶硅栅极结构图案化之后存在的残余多晶硅以及电容器，多晶硅顶板的风险。

10. 发明授权

US06297132B1 Process to control the lateral doping profile of an implanted channel region 有权
标题翻译：控制植入通道区域的横向掺杂分布的方法
公开(公告)号：US06297132B1
公开(公告)日：2001-10-02
申请号：US09498978
申请日：2000-02-07
申请人： Jiong Zhang , Kai Shao , Shao-Fu Sanford Chu
发明人： Jiong Zhang , Kai Shao , Shao-Fu Sanford Chu
IPC分类号： H01L21425
CPC分类号： H01L29/66537 , H01L29/66553 , H01L29/6659 , H01L29/7833
摘要： A process for fabricating a MOSFET device, featuring a narrow lateral delta doping, or a narrow anti-punchthrough region, located in the center of the MOSFET channel region, has been developed. The process features formation of the narrow, anti-punchthrough region, via use of an ion implantation procedure, performed using an opening, comprised with sidewall spacers, as an implant mask. After formation of the narrow, anti-punchthrough region, the sidewall spacers are removed, and a gate insulator layer, and a polysilicon gate structure, are formed in the spacerless opening, defining a channel region wider than the narrow, anti-punchthrough region.
摘要翻译：已经开发了一种制造MOSFET器件的工艺，其具有窄的侧向delta掺杂或位于MOSFET沟道区域的中心的窄反穿通区域。该方法的特征在于，通过使用离子注入程序，使用包括侧壁间隔件的开口作为植入物掩模来执行窄的抗穿透区域的形成。在形成窄的防穿透区域之后，去除侧壁间隔物，并且在无间隔开口中形成栅极绝缘体层和多晶硅栅极结构，限定比窄的反穿通区域宽的沟道区域。

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