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1. 发明申请

US20120313176A1 Buried Sublevel Metallizations for Improved Transistor Density 有权
标题翻译：用于改善晶体管密度的埋层次级金属化
公开(公告)号：US20120313176A1
公开(公告)日：2012-12-13
申请号：US13154548
申请日：2011-06-07
申请人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
IPC分类号： H01L27/088 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/76801 , H01L21/76816 , H01L21/76895 , H01L21/823871
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供第一和第二晶体管元件之间的电连接。

2. 发明授权

US08941182B2 Buried sublevel metallizations for improved transistor density 有权
标题翻译：埋层次级金属化，以提高晶体管密度
公开(公告)号：US08941182B2
公开(公告)日：2015-01-27
申请号：US13154548
申请日：2011-06-07
申请人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/768 , H01L21/8238
CPC分类号： H01L21/823475 , H01L21/76801 , H01L21/76816 , H01L21/76895 , H01L21/823871
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供第一和第二晶体管元件之间的电连接。

3. 发明授权

US08492217B2 Methods of forming conductive contacts with reduced dimensions 有权
标题翻译：形成尺寸减小的导电触点的方法
公开(公告)号：US08492217B2
公开(公告)日：2013-07-23
申请号：US13237011
申请日：2011-09-20
申请人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
IPC分类号： H01L21/8238
CPC分类号： H01L29/665 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L29/6659 , H01L29/7833
摘要： Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.
摘要翻译：本文公开了形成具有减小的尺寸的导电触点和结合这种导电触点的各种半导体器件的各种方法。在一个示例中，本文公开的一种方法包括在半导体衬底上形成绝缘材料层，其中材料层具有第一厚度，在具有第一厚度的材料层中形成多个接触开口并形成有机材料在每个接触开口的至少一部分中。该说明性方法还包括以下步骤：在形成有机材料之后，进行蚀刻工艺，以在绝缘材料层的第一厚度减小至小于第一厚度的第二厚度之后，在进行蚀刻工艺之后，来自接触开口的有机材料，并在每个接触开口中形成导电接触。

4. 发明申请

US20130072016A1 METHODS OF FORMING CONDUCTIVE CONTACTS WITH REDUCED DIMENSIONS 有权
标题翻译：形成具有减小尺寸的导电性接触的方法
公开(公告)号：US20130072016A1
公开(公告)日：2013-03-21
申请号：US13237011
申请日：2011-09-20
申请人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
IPC分类号： H01L21/28
CPC分类号： H01L29/665 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L29/6659 , H01L29/7833
摘要： Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.
摘要翻译：本文公开了形成具有减小的尺寸的导电触点和结合这种导电触点的各种半导体器件的各种方法。在一个示例中，本文公开的一种方法包括在半导体衬底上形成绝缘材料层，其中材料层具有第一厚度，在具有第一厚度的材料层中形成多个接触开口并形成有机材料在每个接触开口的至少一部分中。该说明性方法还包括以下步骤：在形成有机材料之后，进行蚀刻工艺，以在绝缘材料层的第一厚度减小至小于第一厚度的第二厚度之后，在进行蚀刻工艺之后，来自接触开口的有机材料，并在每个接触开口中形成导电接触。

5. 发明授权

US07642158B2 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07642158B2
公开(公告)日：2010-01-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

6. 发明申请

US20070048951A1 Method for production of semiconductor memory devices 审中-公开
标题翻译：半导体存储器件的制造方法
公开(公告)号：US20070048951A1
公开(公告)日：2007-03-01
申请号：US11216526
申请日：2005-08-31
申请人： Hocine Boubekeur , Dominik Olligs , Torsten Mueller , Christoph Kleint , David Pritchard
发明人： Hocine Boubekeur , Dominik Olligs , Torsten Mueller , Christoph Kleint , David Pritchard
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.
摘要翻译：介质光栅形成在字线堆叠之间。间隔件被施加到字线堆叠和介质光栅的侧壁。在间隔物之间的开口中，硅在源/漏区的上表面上外延生长，其被注入自对准到字线堆叠。在生长的硅上形成硅化物，并且施加和构造金属层以形成局部互连，其将源极/漏极区域连接到高位线。

7. 发明授权

US07521351B2 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US07521351B2
公开(公告)日：2009-04-21
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

8. 发明申请

US20070077748A1 Method for forming a semiconductor product and semiconductor product 审中-公开
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070077748A1
公开(公告)日：2007-04-05
申请号：US11241877
申请日：2005-09-30
申请人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
发明人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
IPC分类号： H01L21/4763 , H01L21/3205 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76838 , H01L27/11521 , H01L27/11568
摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).
摘要翻译：半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

9. 发明授权

US08021933B2 Integrated circuit including structures arranged at different densities and method of forming the same 有权
标题翻译：集成电路包括以不同密度排列的结构及其形成方法
公开(公告)号：US08021933B2
公开(公告)日：2011-09-20
申请号：US11847095
申请日：2007-08-29
申请人： Dominik Olligs , Joachim Deppe , David Pritchard , Christoph Kleint
发明人： Dominik Olligs , Joachim Deppe , David Pritchard , Christoph Kleint
IPC分类号： H01L21/82
CPC分类号： H01L27/105 , H01L21/31144 , H01L21/76816 , H01L21/76897 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.
摘要翻译：形成集成电路的方法包括在集成电路的第一部分中形成第一结构，并且在第二部分中形成比第一结构更密集布置的第二结构。第一和第二结构由使用光掩模的光刻工艺定义。光掩模中的至少一个在第一区域中包括用于支撑第一结构的定义的两个开口和用于支撑第二结构的定义的第二区域中的开口。

10. 发明授权

US08009477B2 Integrated circuit and method of forming an integrated circuit 有权
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US08009477B2
公开(公告)日：2011-08-30
申请号：US12182714
申请日：2008-07-30
申请人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
发明人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
IPC分类号： G11C11/40 , H01L27/088 , H01L29/78 , H01L21/4763
CPC分类号： G11C5/063 , H01L21/76804 , H01L21/76807 , H01L21/76813
摘要： An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.
摘要翻译：集成电路和形成集成电路的方法。一个实施例包括形成在载体的表面上方的导线。在垂直于载体表面的方向上的导线的侧壁的斜面显示出不连续性，并且导电线的上部的宽度大于下部的对应宽度。

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