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1. 发明申请

US20070026606A1 METHOD AND STRUCTURE FOR FABRICATING NON VOLATILE MEMORY ARRAYS 失效
标题翻译：用于制造非挥发性记忆阵列的方法和结构
公开(公告)号：US20070026606A1
公开(公告)日：2007-02-01
申请号：US11280529
申请日：2005-11-15
申请人： Kai Chou , Harry Laun , Kenlin Huang , J.C. Young , Arthur Wang
发明人： Kai Chou , Harry Laun , Kenlin Huang , J.C. Young , Arthur Wang
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate. An HDP plasma dielectric is formed overlying the common buried bitline to a height within a vicinity of a first surface of the first word gate and a second surface of the second word gate. In a preferred embodiment, the device has a planarized surface formed from a portion of the HDP plasma dielectric, the first surface, and the second surface. A word line is overlying the planarized surface. The word line is coupled to the first word gate and the second word gate and is overlying the HDP plasma dielectric. The device has a refractory metal layer formed overlying the word line, a hard mask layer overlying the refractory metal layer, and a cap layer formed overlying the hard mask layer. The word line, refractory metal layer, hard mask layer, and cap layer form a planarized structure.
摘要翻译： MONOS集成电路器件。该器件具有包括硅衬底材料和形成在衬底内的浅沟槽隔离区域的半导体衬底。 P型阱区形成在衬底内并与浅沟槽隔离区相邻。所述第一字门包括第一边缘和第二边缘。第一字门包括耦合到第一边缘的第一控制栅极和耦合到第二边缘的第二控制栅极。优选地，第二字门包括第一边缘和第二边缘。第二字门包括耦合到第一边缘的第一控制栅极和耦合到第二边缘的第二控制栅极。在P型阱区域内和第一字栅极的第二边缘与第二字门的第一边缘之间形成公共掩埋位线。 HDP等离子体电介质形成在公共掩埋位线上方至第一字栅极的第一表面附近的高度和第二字门的第二表面。在优选实施例中，该装置具有由HDP等离子体电介质，第一表面和第二表面的一部分形成的平坦化表面。字线覆盖在平坦化表面上。字线耦合到第一字门和第二字门，并且覆盖HDP等离子体电介质。该装置具有形成在字线上方的难熔金属层，覆盖难熔金属层的硬掩模层和覆盖在硬掩模层上的盖层。字线，难熔金属层，硬掩模层和盖层形成平坦化结构。

2. 发明授权

US07172939B1 Method and structure for fabricating non volatile memory arrays 失效
标题翻译：制造非易失性存储器阵列的方法和结构
公开(公告)号：US07172939B1
公开(公告)日：2007-02-06
申请号：US11280529
申请日：2005-11-15
申请人： Kai Cheng Chou , Harry Laun , Kenlin Huang , J. C. Young , Arthur Wang
发明人： Kai Cheng Chou , Harry Laun , Kenlin Huang , J. C. Young , Arthur Wang
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate. An HDP plasma dielectric is formed overlying the common buried bitline to a height within a vicinity of a first surface of the first word gate and a second surface of the second word gate. In a preferred embodiment, the device has a planarized surface formed from a portion of the HDP plasma dielectric, the first surface, and the second surface. A word line is overlying the planarized surface. The word line is coupled to the first word gate and the second word gate and is overlying the HDP plasma dielectric. The device has a refractory metal layer formed overlying the word line, a hard mask layer overlying the refractory metal layer, and a cap layer formed overlying the hard mask layer. The word line, refractory metal layer, hard mask layer, and cap layer form a planarized structure.
摘要翻译： MONOS集成电路器件。该器件具有包括硅衬底材料和形成在衬底内的浅沟槽隔离区域的半导体衬底。 P型阱区形成在衬底内并与浅沟槽隔离区相邻。所述第一字门包括第一边缘和第二边缘。第一字门包括耦合到第一边缘的第一控制栅极和耦合到第二边缘的第二控制栅极。优选地，第二字门包括第一边缘和第二边缘。第二字门包括耦合到第一边缘的第一控制栅极和耦合到第二边缘的第二控制栅极。在P型阱区域内和第一字栅极的第二边缘与第二字门的第一边缘之间形成公共掩埋位线。 HDP等离子体电介质形成在公共掩埋位线上方至第一字栅极的第一表面附近的高度和第二字门的第二表面。在优选实施例中，该装置具有由HDP等离子体电介质，第一表面和第二表面的一部分形成的平坦化表面。字线覆盖在平坦化表面上。字线耦合到第一字门和第二字门，并且覆盖HDP等离子体电介质。该装置具有形成在字线上方的难熔金属层，覆盖难熔金属层的硬掩模层和覆盖在硬掩模层上的盖层。字线，难熔金属层，硬掩模层和盖层形成平坦化结构。

3. 发明申请

US20070126052A1 Method and apparatus for strapping the control gate and the bit line of a MONOS memory array 审中-公开
标题翻译：用于捆绑MONOS存储器阵列的控制栅极和位线的方法和装置
公开(公告)号：US20070126052A1
公开(公告)日：2007-06-07
申请号：US11292941
申请日：2005-12-01
申请人： Harry Luan , J.C. Young , Arthur Wang , K.C. Chou , Kenlin Huang
发明人： Harry Luan , J.C. Young , Arthur Wang , K.C. Chou , Kenlin Huang
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and patterning the word gate poly layer and the first dielectric layer to form an array of word gate structures. The method further includes forming a poly plug layer and patterning the poly plug layer to form a plurality of poly plugs surrounded in the plane of the substrate on three sides, forming a plurality of control gates, forming a second dielectric layer, planarizing the second dielectric layer using a chemical-mechanical polishing process, and depositing a metal layer to provide electrical contact to the word gate structures.
摘要翻译：一种制造非易失性半导体存储器的方法。该方法包括在衬底上形成字门多晶层，其中衬底的上表面限定衬底的平面。该方法还包括形成耦合到字门多晶层的第一介电层，并且对门字多晶层和第一介电层进行构图以形成字门结构的阵列。该方法还包括形成多晶硅塞层并构图多晶硅塞层以形成多个在三面的基片的平面中包围的多晶硅塞，形成多个控制栅极，形成第二介电层，平面化第二电介质层，并且沉积金属层以提供与字栅结构的电接触。

4. 发明申请

US20050260857A1 Method and resulting structure for PCMO film to obtain etching rate and mask to selectively by inductively coupled plasma 有权
标题翻译： PCMO薄膜的方法和结果可通过电感耦合等离子体选择性地获得蚀刻速率和掩模
公开(公告)号：US20050260857A1
公开(公告)日：2005-11-24
申请号：US10854755
申请日：2004-05-24
申请人： Kenlin Huang , K.C. Chou , Harry Luan , J.C. Young , Arthur Wang
发明人： Kenlin Huang , K.C. Chou , Harry Luan , J.C. Young , Arthur Wang
IPC分类号： H01L21/302 , H01L27/24 , H01L45/00
CPC分类号： H01L45/04 , H01L27/2409 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.
摘要翻译：电感耦合等离子体源的创新方法具有高选择性和蚀刻速率。优选地，本发明包括使用等离子体化学的方法，该方法被分为主蚀刻步骤（例如，Cl 2→H + HBr + C→S→S + ））（例如，HBr + Ar）的气体组合和过蚀刻步骤。主蚀刻步骤提供更快的蚀刻速率和选择性，而过蚀刻步骤将降低蚀刻速率并确保桁条和残留物的去除而不侵蚀底层。

5. 发明授权

US07186658B2 Method and resulting structure for PCMO film to obtain etching rate and mask to selectively by inductively coupled plasma 有权
标题翻译： PCMO薄膜的方法和结果可通过电感耦合等离子体选择性地获得蚀刻速率和掩模
公开(公告)号：US07186658B2
公开(公告)日：2007-03-06
申请号：US10854755
申请日：2004-05-24
申请人： Kenlin Huang , Kaicheng Chou , Harry Luan , Jein-Chen Young , Arthur Wang
发明人： Kenlin Huang , Kaicheng Chou , Harry Luan , Jein-Chen Young , Arthur Wang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L45/04 , H01L27/2409 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.
摘要翻译：电感耦合等离子体源的创新方法具有高选择性和蚀刻速率。优选地，本发明包括使用等离子体化学的方法，该方法被分为主蚀刻步骤（例如，Cl 2→H + HBr + C→S→S + ））（例如，HBr + Ar）的气体组合和过蚀刻步骤。主蚀刻步骤提供更快的蚀刻速率和选择性，而过蚀刻步骤将降低蚀刻速率并确保桁条和残留物的去除而不侵蚀底层。

6. 发明授权

US07408212B1 Stackable resistive cross-point memory with schottky diode isolation 有权
标题翻译：具有肖特基二极管隔离的可堆叠电阻交叉点存储器
公开(公告)号：US07408212B1
公开(公告)日：2008-08-05
申请号：US10777560
申请日：2004-02-11
申请人： Harry S. Luan , Jein-Chen Young , Arthur Wang , Kai-Cheng Chou , Kenlin Huang
发明人： Harry S. Luan , Jein-Chen Young , Arthur Wang , Kai-Cheng Chou , Kenlin Huang
IPC分类号： H01L29/76
CPC分类号： G11C13/0007 , G11C13/003 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： An electrically programmable, non-volatile resistive memory includes an array of memory cells, a plurality of bit lines, and a plurality of word lines. Each memory cell comprises a resistive element and a Schottky diode coupled in series and having first and second terminals. Each bit line couples to the first terminal of all memory cells in a respective column of the array. Each word line couples to the second terminal of all memory cells in a respective row of the array. The resistive element for each memory cell may be formed with a film of a perovskite material (e.g., Pr0.7Ca0.3MnO3). The Schottky diode for each memory cell may be formed by a thin film of amorphous silicon. The films for the resistive element and Schottky diode for each memory cell may be stacked in a compact island at the cross point between a bit line and a word line.
摘要翻译：电可编程的非易失性电阻存储器包括存储器单元阵列，多个位线和多个字线。每个存储单元包括串联耦合并具有第一和第二端子的电阻元件和肖特基二极管。每个位线耦合到阵列的相应列中的所有存储器单元的第一端。每个字线耦合到阵列的相应行中的所有存储器单元的第二端子。用于每个存储单元的电阻元件可以由钙钛矿材料（例如，Pr 0.7 N 0.3 Mn 0.3 O 3）的膜形成。每个存储单元的肖特基二极管可以由非晶硅薄膜形成。用于每个存储单元的电阻元件和肖特基二极管的膜可以堆叠在位线和字线之间的交叉点处的紧凑岛中。

7. 发明申请

US20100327557A1 Electric wheelchair 有权
标题翻译：电动轮椅
公开(公告)号：US20100327557A1
公开(公告)日：2010-12-30
申请号：US12457866
申请日：2009-06-24
申请人： Arthur Wang
发明人： Arthur Wang
IPC分类号： A61G5/10
CPC分类号： A61G5/045 , A61G5/085 , A61G5/0891 , A61G5/1059 , A61G5/1089
摘要： An electric wheelchair is disclosed. The electric wheelchair includes a main frame correspondingly pivoted with a foldable chair while the folding of the chair connects with an accessory tip wheel. Moreover, the main frame is disposed with main wheels and a front wheel set arranged on front of the main wheel correspondingly on each of two sides thereof. A footrest that is pulled out or stored in the main frame is arranged between the two front wheel sets. In use, the footrest is pulled out of the main frame and the chair is moved and unfolded. At the same time, the accessory tip wheel tilted a little angle is extended out of the main frame by a connecting member. Thereby the problem caused by movement of the center of gravity of the wheelchair while moving can be solved and the safety of users is ensured.
摘要翻译：公开了一种电动轮椅。电动轮椅包括相当于可折叠椅子枢转的主框架，而椅子的折叠与附件尖端轮连接。此外，主框架配置有主轮和前轮组，其相应地在主轮的两侧分别布置在主轮的前面。在两个前轮组之间布置有被拉出或存储在主框架中的搁脚板。在使用中，搁脚板被拉出主框架，椅子被移动和展开。同时，倾斜一点角度的附件尖端轮由连接构件延伸出主框架。从而可以解决移动时轮椅重心运动引起的问题，确保用户的安全。

8. 发明申请

US20100187034A1 Fixing device for a foldable chassis of an electric walk-substituting vehicle 有权
标题翻译：电动步态车的可折叠底盘的固定装置
公开(公告)号：US20100187034A1
公开(公告)日：2010-07-29
申请号：US12320499
申请日：2009-01-28
申请人： Arthur Wang
发明人： Arthur Wang
IPC分类号： B62D63/02
CPC分类号： B62K15/008 , B62K5/007
摘要： A walk-substituting vehicle includes a foldable chassis, a steering mechanism, a seat assembly, and a fixing device, which is movable to a fastening portion to prevent the chassis from folding from an in-use position; the chassis includes a main part and a footrest part; the vehicle can be moved to a folded configuration, wherein the chassis is folded, and the steering mechanism and the seat assembly lie on the chassis; the fixing device includes a pulling member pivoted on the footrest part, a joining member pivoted on the pulling member, and a pushing member joined on and slideable along a receiving recessed portion of the pulling member; when the fixing device is in the fastening position, the joining member will be hooked over the main part of the chassis, and the pushing member engaged with the joining member to prevent the joining member from pivoting relative to the pulling member.
摘要翻译：步行代替车辆包括可折叠底盘，转向机构，座椅组件和固定装置，其可移动到紧固部分以防止底架从使用位置折叠; 底盘包括主要部分和脚踏部分; 车辆可以移动到折叠的构造，其中底盘被折叠，并且转向机构和座椅组件位于底盘上; 所述固定装置包括在所述脚踏部上枢转的牵引构件，在所述牵引构件上枢转的接合构件，以及沿所述牵引构件的容纳凹部接合并可滑动的推动构件; 当固定装置处于紧固位置时，接合构件将被钩在底盘的主要部分上，并且推动构件与接合构件接合以防止接合构件相对于拉动构件枢转。

9. 发明申请

US20100181124A1 Folding and fixing device for a seat of an electric walk-substituting vehicle 有权
标题翻译：电动步行车辆座椅的折叠和固定装置
公开(公告)号：US20100181124A1
公开(公告)日：2010-07-22
申请号：US12320145
申请日：2009-01-21
申请人： Arthur Wang
发明人： Arthur Wang
IPC分类号： A61G5/08 , A61G5/04 , B60K1/00 , B60N2/30 , B60N2/04 , A61G5/10
CPC分类号： B60N2/3011 , A61G5/045 , A61G5/08 , A61G5/085 , A61G5/0883 , A61G5/0891 , A61G5/1051 , B60N2/3065 , B60N2/309 , B60Y2200/84 , B62K5/007 , Y10S180/907
摘要： An electric walk-substituting vehicle includes a chassis, a seat assembly pivoted on upper ends of the connecting rods, a pivotal steering mechanism, and a folding and fixing device, which will fix the connecting rods after the seat assembly is moved to either of raised in-use and lowered not-in-use positions; the seat assembly includes connecting rods pivoted on the chassis; the folding and fixing device includes two position-limiting plates, which are secured on the connecting rods to pivot together with the connecting rods; the position-limiting plates each have first and second holes; the folding and fixing device includes a pressing and moving mechanism with two insertion rods; the insertion rods will pass into the first holes to engage the position-limiting plates after the connecting rods are pivoted to the raised in-use position; the insertion rods will pass into the second holes after the connecting rods are pivoted to the not-in-use position.
摘要翻译：电动步行车辆包括底盘，枢转在连杆上端的座椅组件，枢转转向机构和折叠和固定装置，其将座椅组件移动到升高的任何一个之后将连接杆固定在使用和降低不使用的职位; 座椅组件包括在底盘上枢转的连杆; 折叠和固定装置包括两个限位板，它们固定在连接杆上以与连杆一起枢转; 位置限制板各自具有第一和第二孔; 折叠和固定装置包括具有两个插入杆的按压和移动机构; 在连接杆枢转到升高的使用位置之后，插入杆将进入第一孔以接合限位板; 在连接杆枢转到不使用位置之后，插入杆将进入第二个孔。

10. 发明申请

US20080005982A1 Satellite ready building and method for forming the same 有权
标题翻译：卫星就绪建筑及其形成方法
公开(公告)号：US20080005982A1
公开(公告)日：2008-01-10
申请号：US11649480
申请日：2007-01-04
申请人： Arthur Wang
发明人： Arthur Wang
IPC分类号： E04C2/52
CPC分类号： H01Q1/1221 , H01Q1/42 , H01Q3/06 , H01Q13/28 , H01Q21/061
摘要： A satellite ready building comprises a plurality of studs and satellite wires positioned adjacent to the studs having a first termination and a second termination. A connector is coupled to the second termination of the wires. The first termination is coupled through the roof or the siding of the building. Drywall is installed in the house after the wires are installed. The first termination may be installed in a radome positioned on the roof of the building.
摘要翻译：卫星就绪建筑物包括多个螺栓和卫星导线，这些螺柱和卫星导线与具有第一终端和第二终端的柱相邻。连接器耦合到电线的第二终端。第一个终端通过屋顶或建筑物的侧板耦合。电线安装后，房屋内装有干墙。第一个终端可以安装在位于建筑物屋顶上的天线罩中。

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