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1. 发明申请

US20070126052A1 Method and apparatus for strapping the control gate and the bit line of a MONOS memory array 审中-公开
标题翻译：用于捆绑MONOS存储器阵列的控制栅极和位线的方法和装置
公开(公告)号：US20070126052A1
公开(公告)日：2007-06-07
申请号：US11292941
申请日：2005-12-01
申请人： Harry Luan , J.C. Young , Arthur Wang , K.C. Chou , Kenlin Huang
发明人： Harry Luan , J.C. Young , Arthur Wang , K.C. Chou , Kenlin Huang
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and patterning the word gate poly layer and the first dielectric layer to form an array of word gate structures. The method further includes forming a poly plug layer and patterning the poly plug layer to form a plurality of poly plugs surrounded in the plane of the substrate on three sides, forming a plurality of control gates, forming a second dielectric layer, planarizing the second dielectric layer using a chemical-mechanical polishing process, and depositing a metal layer to provide electrical contact to the word gate structures.
摘要翻译：一种制造非易失性半导体存储器的方法。该方法包括在衬底上形成字门多晶层，其中衬底的上表面限定衬底的平面。该方法还包括形成耦合到字门多晶层的第一介电层，并且对门字多晶层和第一介电层进行构图以形成字门结构的阵列。该方法还包括形成多晶硅塞层并构图多晶硅塞层以形成多个在三面的基片的平面中包围的多晶硅塞，形成多个控制栅极，形成第二介电层，平面化第二电介质层，并且沉积金属层以提供与字栅结构的电接触。

2. 发明申请

US20050260857A1 Method and resulting structure for PCMO film to obtain etching rate and mask to selectively by inductively coupled plasma 有权
标题翻译： PCMO薄膜的方法和结果可通过电感耦合等离子体选择性地获得蚀刻速率和掩模
公开(公告)号：US20050260857A1
公开(公告)日：2005-11-24
申请号：US10854755
申请日：2004-05-24
申请人： Kenlin Huang , K.C. Chou , Harry Luan , J.C. Young , Arthur Wang
发明人： Kenlin Huang , K.C. Chou , Harry Luan , J.C. Young , Arthur Wang
IPC分类号： H01L21/302 , H01L27/24 , H01L45/00
CPC分类号： H01L45/04 , H01L27/2409 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.
摘要翻译：电感耦合等离子体源的创新方法具有高选择性和蚀刻速率。优选地，本发明包括使用等离子体化学的方法，该方法被分为主蚀刻步骤（例如，Cl 2→H + HBr + C→S→S + ））（例如，HBr + Ar）的气体组合和过蚀刻步骤。主蚀刻步骤提供更快的蚀刻速率和选择性，而过蚀刻步骤将降低蚀刻速率并确保桁条和残留物的去除而不侵蚀底层。

3. 发明授权

US07186658B2 Method and resulting structure for PCMO film to obtain etching rate and mask to selectively by inductively coupled plasma 有权
标题翻译： PCMO薄膜的方法和结果可通过电感耦合等离子体选择性地获得蚀刻速率和掩模
公开(公告)号：US07186658B2
公开(公告)日：2007-03-06
申请号：US10854755
申请日：2004-05-24
申请人： Kenlin Huang , Kaicheng Chou , Harry Luan , Jein-Chen Young , Arthur Wang
发明人： Kenlin Huang , Kaicheng Chou , Harry Luan , Jein-Chen Young , Arthur Wang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L45/04 , H01L27/2409 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.
摘要翻译：电感耦合等离子体源的创新方法具有高选择性和蚀刻速率。优选地，本发明包括使用等离子体化学的方法，该方法被分为主蚀刻步骤（例如，Cl 2→H + HBr + C→S→S + ））（例如，HBr + Ar）的气体组合和过蚀刻步骤。主蚀刻步骤提供更快的蚀刻速率和选择性，而过蚀刻步骤将降低蚀刻速率并确保桁条和残留物的去除而不侵蚀底层。

4. 发明申请

US20070230232A1 MEMORY TRANSISTOR GATE OXIDE STRESS RELEASE AND IMPROVED RELIABILITY 有权
标题翻译：内存晶闸管氧化物应力释放和改进的可靠性
公开(公告)号：US20070230232A1
公开(公告)日：2007-10-04
申请号：US11759050
申请日：2007-06-06
申请人： David Fong , Jianguo Wang , Jack Peng , Harry Luan
发明人： David Fong , Jianguo Wang , Jack Peng , Harry Luan
IPC分类号： G11C17/00
CPC分类号： G11C7/08 , G11C7/18 , G11C16/28 , G11C2207/061 , G11C2207/065
摘要： Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.
摘要翻译：公开了减少存储晶体管的氧化物应力和提高可靠性的方法和装置。存储晶体管栅极对读取信号的持续时间和频率显着降低。在一些实施例中，在短的读取周期之后，只要后续读取尝试被引导到相同的存储器单元，存储器单元的内容被锁存和维持。在这些实施例中，读周期只需要足够长的时间来锁存单元的存储器内容，并且只要随后的读取尝试针对相同的存储单元，将使用锁存值而不是重复读取处理。

5. 发明申请

US20070133334A1 Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit 有权
标题翻译：存储单元包括OTP非易失性存储单元和SRAM单元
公开(公告)号：US20070133334A1
公开(公告)日：2007-06-14
申请号：US11356805
申请日：2006-02-17
申请人： Jack Peng , David Fong , Harry Luan , Jianguo Wang , Zhongshang Liu
发明人： Jack Peng , David Fong , Harry Luan , Jianguo Wang , Zhongshang Liu
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C2216/26
摘要： Memory cells comprising an SRAM and an OTP memory unit are disclosed that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. Disclosed concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of disclosed memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.
摘要翻译：公开了包括SRAM和OTP存储器单元的存储器单元，其结合了这两种技术的优点，并且可以通过标准CMOS制造来制造而不需要额外的掩蔽。公开的概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。除了其他优点之外，所公开的存储单元的SRAM部分允许对单元进行无数次编程，这在例如原型设计期间是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

6. 发明申请

US20070206417A1 MEMORY TRANSISTOR GATE OXIDE STRESS RELEASE AND IMPROVED RELIABILITY 有权
公开(公告)号：US20070206417A1
公开(公告)日：2007-09-06
申请号：US11368576
申请日：2006-03-06
申请人： David Fong , Jianguo Wang , Jack Peng , Harry Luan
发明人： David Fong , Jianguo Wang , Jack Peng , Harry Luan
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C7/08 , G11C7/18 , G11C16/28 , G11C2207/061 , G11C2207/065
摘要： Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

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