专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2005020062A1 DYNAMIC MEMORY BUFFER 审中-公开
标题翻译：动态内存缓冲区
公开(公告)号：WO2005020062A1
公开(公告)日：2005-03-03
申请号：PCT/IB2004/051405
申请日：2004-08-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BURCHARD, Artur, T. , LUITJENS, Steven, B.
发明人： BURCHARD, Artur, T. , LUITJENS, Steven, B.
IPC分类号： G06F5/06
CPC分类号： G06F5/10 , G06F2205/063
摘要： There is described a dynamic memory buffer (30, 210) for buffering between one or more software applications (40) executing on computing means and one or more data generating and/or receiving devices (20) in communication through the buffer (30, 210) to the one or more applications (40), the buffer (30, 210) including buffer managing means (210) for controlling allocation of one or more portions of the buffer (30) to the one or more applications (40) so as to reduce power dissipation occurring within the one or more devices (20).
摘要翻译：描述了用于在计算装置上执行的一个或多个软件应用程序（40）和通过缓冲器（30,210）进行通信的一个或多个数据生成和/或接收装置（20）之间进行缓冲的动态存储器缓冲器（30,210））到所述一个或多个应用（40）中，所述缓冲器（30,210）包括用于控制所述缓冲器（30）的一个或多个部分到所述一个或多个应用（40）的分配的缓冲器管理装置（210），以便以减少在所述一个或多个设备（20）内发生的功率耗散。

2. 发明申请

WO2008007273A2 A DEVICE AND A METHOD FOR MANAGING POWER CONSUMPTION OF A PLURALITY OF DATA PROCESSING UNITS 审中-公开
标题翻译：管理多个数据处理单元的功率消耗的装置和方法
公开(公告)号：WO2008007273A2
公开(公告)日：2008-01-17
申请号：PCT/IB2007/052463
申请日：2007-06-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , YERMALAYEU, Siarhei , MESUT, Ozcan , LUITJENS, Steven, B. , VAN GASSEL, Jozef, P. , BURCHARD, Artur, T. , DE NIJS, Gilein
发明人： YERMALAYEU, Siarhei , MESUT, Ozcan , LUITJENS, Steven, B. , VAN GASSEL, Jozef, P. , BURCHARD, Artur, T. , DE NIJS, Gilein
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/329 , Y02D10/24
摘要： A device and a method for managing power consumption of a plurality of data processing units. A scheduler (280) schedules a first process step for a first data processing unit (200) consuming a high power within a first deadline and a second process step for a second data processing unit (240) also consuming a high power within a second deadline. The scheduler further schedules the first process step and the second process step such that the two process steps do not occur concurrently thereby reducing the peak power draw from a power supply whilst preserving deadlines. This is particularly beneficial in battery-operated equipment, such as portable electronic multimedia devices, since peak power drain has been found to be an important factor in determining the battery capacity.
摘要翻译：用于管理多个数据处理单元的功耗的设备和方法。调度器（280）调度在第一期限内消耗高功率的第一数据处理单元（200）的第一处理步骤和在第二期限内消耗高功率的第二数据处理单元（240）的第二处理步骤。调度器进一步调度第一处理步骤和第二处理步骤，使得两个处理步骤不同时发生，从而减少从电源提供的峰值功率，同时保持最终期限。这对电池供电的设备特别有用，例如便携式电子多媒体设备，因为已经发现峰值功耗是决定电池容量的重要因素。

3. 发明申请

WO2005010768A1 INTEGRATED CIRCUIT WITH DYNAMIC COMMUNICATION SERVICE SELECTION 审中-公开
标题翻译：集成电路与动态通信服务选择
公开(公告)号：WO2005010768A1
公开(公告)日：2005-02-03
申请号：PCT/IB2004/051269
申请日：2004-07-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BURCHARD, Artur, T. , HARMSZE, Françoise, J. , KENTER, Harm, J., H., N.
发明人： BURCHARD, Artur, T. , HARMSZE, Françoise, J. , KENTER, Harm, J., H., N.
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： An integrated circuit comprising a plurality of modules (M1 to M5, CPU) for processing applications, a global memory (GM), which can be shared by said plurality of modules (M1 to M5, CPU), an interconnect means (IM) for interconnecting said modules (M 1 to M5, CPU) and said global memory (GM) based on a plurality of communication services (C1, C2) is provided. Said integrated circuit further comprises at least one communication managing unit (CMU) for managing the communication between said plurality of modules (M1 to M5), wherein said communication managing unit (CMU) receives a request for a communication between at least two of said modules (M1 to M5, CPU) and dynamically selects one of said plurality of communication services (C 1, C2) as basis for the requested communication between said modules (MI to M5, CPU).
摘要翻译：一种集成电路，包括用于处理应用的多个模块（M1至M5，CPU），可由所述多个模块（M1至M5，CPU）共享的全局存储器（GM），用于提供了基于多个通信服务（C1，C2）将所述模块（M 1至M 5，CPU）和所述全局存储器（GM）互连。所述集成电路还包括用于管理所述多个模块（M1至M5）之间的通信的至少一个通信管理单元（CMU），其中所述通信管理单元（CMU）接收至少两个所述模块之间的通信请求（M1至M5，CPU）并且动态地选择所述多个通信服务（C 1，C 2）中的一个作为所述模块（MI至M5，CPU）之间所请求的通信的基础。

4. 发明申请

WO2005088468A3 INTEGRATED CIRCUIT AND METHOD FOR MEMORY ACCESS CONTROL 审中-公开
公开(公告)号：WO2005088468A3
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050816
申请日：2005-03-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BURCHARD, Artur, T. , HARMSZE, Francoise, J.
发明人： BURCHARD, Artur, T. , HARMSZE, Francoise, J.
IPC分类号： G06F13/14 , G06F13/16
摘要： An integrated circuit comprising at least one processing module (PROC) for processing an application (APL) requiring specific communication parameter, at least one dynamic random access memory means (MM) for storing data, wherein the memory means (MM) is operable by a plurality of predefined operating modes, is provided. Additionally, at least one memory access selection means (SM) for selecting one of said plurality of predefined operating modes based on said communication parameters and at least one memory controller (MC) for controlling the access of said at least one dynamic random access memory means (MM) according to said predefined operating modes selected by said memory access selecting means (SM) is provided. Each of said memory controller (MC) are associated to one of the dynamic random access means (MM). An interconnect means (IM) couples the processing modules (PROC) and the memory controller (MC), such that the communication over the interconnect means (IM) is achieved.

5. 发明申请

WO2005010759A1 INTEGRATED CIRCUIT WITH DYNAMIC MEMORY ALLOCATION 审中-公开
标题翻译：具有动态记忆分配的集成电路
公开(公告)号：WO2005010759A1
公开(公告)日：2005-02-03
申请号：PCT/IB2004/051241
申请日：2004-07-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HARMSZE, Françoise, J. , BURCHARD, Artur, T. , KENTER, Harm, J, H., N.
发明人： HARMSZE, Françoise, J. , BURCHARD, Artur, T. , KENTER, Harm, J, H., N.
IPC分类号： G06F12/02
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862 , Y02D10/13
摘要： An integrated circuit comprising a plurality of modules (M) for processing applications is provided, wherein each of said modules comprise a local memory (LM). The integrated circuit further comprises a global memory (GM), which can be shared between the plurality of modules (M), and an interconnect means (IM) for interconnecting said modules (M) and said global memory (GM). A memory managing unit (MMU) is associated to each of said modules (M) and determines whether the local memory (LM) provides sufficient memory space for the currently processed application. If this is not the case, the memory managing unit (MMU) requests a global buffer (FB) in said global memory (GM) to be exclusively reserved for the processing data of its associated module (M). Accordingly, by using the local memory (LM), whenever possible, before data is outsourced to the global memory (GM), power as well as bandwidth of the interconnect means can be saved. Furthermore, sufficient flexibility is introduced to the system on-chip to enable running applications that demand more local resources e. g. local memory, than are available in the subsystems or modules (M), without having the need to design the subsystems or modules for worst case scenarios. Especially, when the worst-case demands are much higher than the average case, the cost advantage can be significant.
摘要翻译：提供一种包括用于处理应用的多个模块（M）的集成电路，其中每个所述模块包括本地存储器（LM）。集成电路还包括可以在多个模块（M）之间共享的全局存储器（GM）和用于互连所述模块（M）和所述全局存储器（GM）的互连装置（IM）。存储器管理单元（MMU）与每个所述模块（M）相关联并且确定本地存储器（LM）是否为当前处理的应用提供足够的存储器空间。如果不是这种情况，则存储器管理单元（MMU）请求全局存储器（GM）中的全局缓冲器（FB）专用于其关联的模块（M）的处理数据。因此，通过使用本地存储器（LM），只要可能，在将数据外包给全局存储器（GM）之前，可以节省功率以及互连装置的带宽。此外，片上系统引入了足够的灵活性，以便能够运行需要更多本地资源的应用程序。 G。本地存储器，而不是在子系统或模块（M）中可用，而不需要为最坏情况设计子系统或模块。特别是当最坏情况要求远高于平均情况时，成本优势可能会很大。

6. 发明申请

WO2005010781A1 AN OBJECT CREATION STRATEGY FOR SIMULATOR MODULES 审中-公开
标题翻译：模拟器模块的对象创建策略
公开(公告)号：WO2005010781A1
公开(公告)日：2005-02-03
申请号：PCT/IB2004/051221
申请日：2004-07-14
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KENTER, Harm, J., H., N. , HARMSZE, Francoise, J. , BURCHARD, Artur, T.
发明人： KENTER, Harm, J., H., N. , HARMSZE, Francoise, J. , BURCHARD, Artur, T.
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a method of performing a simulation based on a simulation model, wherein the simulation model comprises a number of interconnected simulation objects, where at least part of the simulation objects is adapted to be sim+ted based on simulation code defined in accessible modules identified by a module ID, and where at least a part of said accessible modules has an attached module specific object creator defining how the simulation code in the module is to be handled when simulating an object defined by the module, the method of performing the simulation comprising the steps of: initializing the simulation by registering, in a simulation system accessible d ' abase, a link between the module ID and how to access the module specific object creator and accessing said module specific object creator when simulating an object defined by the attached module. Thereby the definition on how the simulation code in the modules is to be handled is no longer inside the simulator, and the kernel of the simulator does not need to be recompiled when adding new modules. Instead, the simulator can just look in the database, which provides the link between the module names from the system model and how to access the module specific object creator.
摘要翻译：本发明涉及一种基于仿真模型执行仿真的方法，其中仿真模型包括多个互连的仿真对象，其中至少部分仿真对象适于基于模拟代码中的定义由模块ID识别的可访问模块，并且其中至少一部分所述可访问模块具有附加的模块特定对象创建者，其定义当模拟由模块定义的对象时模块中的模拟代码如何被处理，执行方法该模拟包括以下步骤：通过在模拟系统可访问的模拟系统中注册模块ID之间的链接以及如何访问模块特定对象创建者并且在模拟由附件模块。因此，如何处理模块中的模拟代码的定义不再在模拟器内，并且在添加新模块时，模拟器的内核不需要重新编译。相反，模拟器只能查看数据库，这提供了来自系统模型的模块名称之间的链接以及如何访问模块特定对象创建者。

7. 发明申请

WO2008117248A1 ELECTRONIC DEVICE AND METHOD DETERMINING A WORKLOAD OF AN ELECTRONIC DEVICE 审中-公开
标题翻译：电子设备和确定电子设备的工作负载的方法
公开(公告)号：WO2008117248A1
公开(公告)日：2008-10-02
申请号：PCT/IB2008/051124
申请日：2008-03-26
申请人： NXP B.V. , BURCHARD, Artur, T. , MEIJER, Rinze, I., M., P.
发明人： BURCHARD, Artur, T. , MEIJER, Rinze, I., M., P.
IPC分类号： G06F1/16
CPC分类号： G06F1/3203 , Y02D10/126
摘要： An electronic device is provided with at least one functional unit (HB) performing a processing, wherein the functional unit (HB) receives a supply current (Isupply). A supply current monitor (SCM) is provided for monitoring the supply current (Isupply) to determine an average supply current (Iavg). A characterization unit (CU) is provided for determining a first relation between the averaged supply current (Iavg) and an operation frequency of the functional unit and/or for determining a second relation between a workload of the functional unit (HB) and the average supply current (Iavg) of the functional unit (HB). Furthermore, a slope calculation unit (SCU) is provided for determining the slope of the first and/or second relation. The operation of the functional unit (HB) is controlled according to the results of the slope calculation unit (SCU).
摘要翻译：电子设备具有执行处理的至少一个功能单元（HB），其中功能单元（HB）接收供电电流（Isupply）。提供电源电流监视器（SCM）用于监视电源电流（Isupply）以确定平均电源电流（Iavg）。提供表征单元（CU），用于确定平均的电源电流（Iavg）和功能单元的操作频率之间的第一关系和/或用于确定功能单元（HB）的工作负载与平均值之间的第二关系供电电流（Iavg）功能单元（HB）。此外，提供斜率计算单元（SCU），用于确定第一和/或第二关系的斜率。功能单元（HB）的操作根据斜率计算单元（SCU）的结果进行控制。

8. 发明申请

WO2008129461A3 ELECTRONIC DEVICE AND METHOD OF PERFORMING A POWER MANAGEMENT IN AN ELECTRONIC DEVICE 审中-公开
公开(公告)号：WO2008129461A3
公开(公告)日：2008-10-30
申请号：PCT/IB2008/051440
申请日：2008-04-15
申请人： NXP B.V. , BURCHARD, Artur, T. , MEIJER, Rinze, I., M., P.
发明人： BURCHARD, Artur, T. , MEIJER, Rinze, I., M., P.
IPC分类号： G06F1/32
摘要： An electronic device is provided which comprises at least one functional unit (HB) for performing a processing. The functional unit (HB) receives a supply current (Isupply). The electronic device furthermore comprises a supply current monitor (SCM) for monitoring the supply current (Isupply) in order to determine an average supply current (Iavg). The electronic device furthermore comprises a characterization unit (CU) for determining a relation between the average supply current (Iavg) and an operating frequency of the functional unit. Furthermore, a slope calculation unit (SCU) is provided to determine the slope of the relation. Moreover, a power management unit (PMU) is provided to control the operation of the functional unit (HB) according to the results of the slope calculation unit (SCU) in order to control the power dissipation of the functional unit (HB).

9. 发明公开

EP1658554A1 DYNAMIC MEMORY BUFFER 审中-公开
标题翻译：动态内存缓冲区
公开(公告)号：EP1658554A1
公开(公告)日：2006-05-24
申请号：EP04744751.1
申请日：2004-08-05
申请人： Koninklijke Philips Electronics N.V.
发明人： BURCHARD, Artur, T. , LUITJENS, Steven, B.
IPC分类号： G06F5/06
CPC分类号： G06F5/10 , G06F2205/063
摘要： There is described a dynamic memory buffer (30, 210) for buffering between one or more software applications (40) executing on computing means and one or more data generating and/or receiving devices (20) in communication through the buffer (30, 210) to the one or more applications (40), the buffer (30, 210) including buffer managing means (210) for controlling allocation of one or more portions of the buffer (30) to the one or more applications (40) so as to reduce power dissipation occurring within the one or more devices (20).

10. 发明公开

EP1728166A2 INTEGRATED CIRCUIT AND METHOD FOR MEMORY ACCESS CONTROL 有权
标题翻译：集成电路和方法实现内存控制
公开(公告)号：EP1728166A2
公开(公告)日：2006-12-06
申请号：EP05708947.6
申请日：2005-03-04
申请人： Koninklijke Philips Electronics N.V.
发明人： BURCHARD, Artur, T. , HARMSZE, Francoise, J.
IPC分类号： G06F13/16
CPC分类号： G06F13/1694 , Y02D10/14
摘要： An integrated circuit comprising at least one processing module (PROC) for processing an application (APL) requiring specific communication parameter, at least one dynamic random access memory means (MM) for storing data, wherein the memory means (MM) is operable by a plurality of predefined operating modes, is provided. Additionally, at least one memory access selection means (SM) for selecting one of said plurality of predefined operating modes based on said communication parameters and at least one memory controller (MC) for controlling the access of said at least one dynamic random access memory means (MM) according to said predefined operating modes selected by said memory access selecting means (SM) is provided. Each of said memory controller (MC) are associated to one of the dynamic random access means (MM). An interconnect means (IM) couples the processing modules (PROC) and the memory controller (MC), such that the communication over the interconnect means (IM) is achieved.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式