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    • 5. 发明申请
    • POWER SAVING OPERATION OF AN APPARATUS WITH A CACHE MEMORY
    • 具有高速缓冲存储器的设备的省电操作
    • WO2005026928A2
    • 2005-03-24
    • PCT/IB2004051602
    • 2004-08-30
    • KONINKL PHILIPS ELECTRONICS NVVAN DER HEIJDEN GERARDUS W T
    • VAN DER HEIJDEN GERARDUS W T
    • G06F1/32
    • G06F1/3225
    • An apparatus that contains an instruction processing circuit (14), a main memory (18) addressable by the instruction processing circuit (14) and a cache memory (16). In a normal mode the cache memory (16) is used to cache a part of data and/or instructions that the instruction processing circuit (14) addresses in the main memory (18) during execution, and to substitute cached data and/or instructions when the instruction processing circuit (14) addresses the data and/or instructions in the main memory (18). The circuit is able to switch to a low power operating mode. Upon the switch an interrupt program for executing a function during operation in the low power operating mode is loaded into the cache memory (16) from the main memory (18). Power supply to the main memory (18) is then switched off, but keeping at least a part of the cache memory (16) continuous to receive power supply. This part ensures that the program of instructions for executing the function is available to the instruction processing circuit. The program is executed from said at least part of the cache memory (16) in the low power operating mode.
    • 一种包含指令处理电路(14),可由指令处理电路(14)寻址的主存储器(18)和高速缓冲存储器(16)的装置。 在正常模式中,高速缓冲存储器(16)用于高速缓存指令处理电路(14)在执行期间在主存储器(18)中寻址的数据和/或指令的一部分,并且将高速缓存的数据和/或指令 当指令处理电路(14)寻址主存储器(18)中的数据和/或指令时。 该电路能够切换到低功率工作模式。 在切换时,用于在低功率操作模式下操作期间执行功能的中断程序从主存储器(18)加载到高速缓冲存储器(16)中。 然后关掉主存储器(18)的供电,但保持至少一部分高速缓冲存储器(16)持续接收电源。 该部分确保用于执行该功能的指令程序可用于指令处理电路。 该程序在低功率操作模式下从所述至少一部分高速缓冲存储器(16)执行。