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1. 发明申请

WO2011008688A3 SCANNER PERFORMANCE COMPARISON AND MATCHING USING DESIGN AND DEFECT DATA 审中-公开
标题翻译：扫描仪性能比较和匹配使用设计和缺陷数据
公开(公告)号：WO2011008688A3
公开(公告)日：2011-05-05
申请号：PCT/US2010041697
申请日：2010-07-12
申请人： KLA TENCOR CORP , PARK ALLEN , CHANG ELLIS , AOKI MASAMI , YOUNG CHRIS CHIH-CHIEN , PLIHAL MARTIN , VAN RIET MICHAEL JOHN
发明人： PARK ALLEN , CHANG ELLIS , AOKI MASAMI , YOUNG CHRIS CHIH-CHIEN , PLIHAL MARTIN , VAN RIET MICHAEL JOHN
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , G03F7/70516 , G03F7/70625 , G03F7/70641 , G03F7/7065
摘要： A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a "no match". Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively.
摘要翻译：描述使用设计和缺陷数据匹配多个扫描仪的系统和方法。使用金色工具处理金色晶圆。使用第二工具处理第二晶片。两种工具都提供对焦/曝光调制。可以比较两个晶片的关键结构的晶片级空间特征，以评估扫描仪的行为。关键结构可以通过在具有相似图案的金色晶片上合并缺陷来识别。在一个实施例中，签名必须在一定百分比内匹配，或者第二工具被表征为“不匹配”。可以以类似的方式比较网状物，其中分别使用金色掩模版和第二掩模版来处理金色和第二晶片。

2. 发明申请

WO2008086282A3 METHODS AND SYSTEMS FOR USING ELECTRICAL INFORMATION FOR A DEVICE BEING FABRICATED ON A WAFER TO PERFORM ONE OR MORE DEFECT-RELATED FUNCTIONS 审中-公开
标题翻译：用于在晶片上制造的器件使用电信息以执行一个或多个缺陷相关功能的方法和系统
公开(公告)号：WO2008086282A3
公开(公告)日：2008-09-12
申请号：PCT/US2008050397
申请日：2008-01-07
申请人： KLA TENCOR CORP , PARK ALLEN , ROSE PETER , CHANG ELLIS , DUFFY BRIAN , MCCORD MARK , ABBOTT GORDON
发明人： PARK ALLEN , ROSE PETER , CHANG ELLIS , DUFFY BRIAN , MCCORD MARK , ABBOTT GORDON
IPC分类号： G01N21/95 , G01N21/956 , G01R31/307 , G01R31/311 , G03F7/20 , G06T7/20 , H01L21/66
CPC分类号： G06T7/0004 , G01N21/8851 , G01N21/956 , G01R31/2894 , G06T2207/30148
摘要： Various methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions are provided. One computer-implemented method includes using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions. The one or more defect-related functions include one or more post-mask, defect-related functions.
摘要翻译：提供了用于将电信息用于在晶圆上制造的器件以执行一个或多个缺陷相关功能的各种方法和系统。一种计算机实现的方法包括使用电信息来制造在晶片上制造的器件以执行一个或多个缺陷相关功能。一个或多个缺陷相关功能包括一个或多个后掩模，缺陷相关功能。

3. 发明申请

WO2013040063A3 DETERMINING DESIGN COORDINATES FOR WAFER DEFECTS 审中-公开
标题翻译：确定缺陷的设计坐标
公开(公告)号：WO2013040063A3
公开(公告)日：2013-06-27
申请号：PCT/US2012054904
申请日：2012-09-12
申请人： KLA TENCOR CORP , CHANG ELLIS , VAN RIET MICHAEL , PARK ALLEN , ZAFAR KHURRAM , BHATTACHARYYA SANTOSH
发明人： CHANG ELLIS , VAN RIET MICHAEL , PARK ALLEN , ZAFAR KHURRAM , BHATTACHARYYA SANTOSH
IPC分类号： H01L21/66
CPC分类号： G06T7/001 , G06T7/74 , G06T2207/30148
摘要： Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.
摘要翻译：提供了用于确定在晶片上检测到的缺陷的设计坐标的方法和系统。一种方法包括对准晶片的设计以通过检查工具对晶片上的多个条带中检测到的缺陷来检查工具图像，基于对准的结果确定每个缺陷在设计坐标中的位置，分别确定缺陷基于检测到每个缺陷的条带（条纹校正因子），每个缺陷的设计坐标以及由检查工具确定的每个缺陷的位置，针对每个多个条带的位置偏移，以及通过对这些缺陷应用适当的条纹校正因子来确定检测工具在多个条中检测到的其他缺陷的设计坐标。

4. 发明申请

WO2012170477A3 USING THREE-DIMENSIONAL REPRESENTATIONS FOR DEFECT-RELATED APPLICATIONS 审中-公开
标题翻译：使用缺陷相关应用的三维表示法
公开(公告)号：WO2012170477A3
公开(公告)日：2013-04-25
申请号：PCT/US2012041019
申请日：2012-06-06
申请人： KLA TENCOR CORP , PARK ALLEN , CHANG ELLIS , AJI PRASHANT A , LANGE STEVEN R
发明人： PARK ALLEN , CHANG ELLIS , AJI PRASHANT A , LANGE STEVEN R
IPC分类号： H01L21/66
CPC分类号： G06F17/5068 , G01N21/9501 , G06F17/50 , G06F17/5009 , G06F2217/12 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method for determining one or more inspection parameters for a wafer inspection recipe is described. The method comprises the steps of: generating a three-dimensional representation of one or more layers of a wafer based on design data; and determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation. The method is performed by a computer system.
摘要翻译：描述了一种用于确定晶片检查配方的一个或多个检查参数的方法。该方法包括以下步骤：基于设计数据生成晶片的一层或多层的三维表示; 以及基于所述三维表示确定用于晶片检查配方的一个或多个检查参数。该方法由计算机系统执行。

5. 发明申请

WO2012016243A8 REGION BASED VIRTUAL FOURIER FILTER 审中-公开
标题翻译：基于区域的虚拟傅里叶滤波器
公开(公告)号：WO2012016243A8
公开(公告)日：2012-09-27
申请号：PCT/US2011046154
申请日：2011-08-01
申请人： KLA TENCOR CORP , GAO LISHENG , WU KENONG , PARK ALLEN , CHANG ELLIS , ZAFAR KHURRAM , HUANG JUNQING JENNY , GU PING , MAHER CHRISTOPHER , CHEN GRACE H , RONG SONGNIAN , WU LIU-MING
发明人： GAO LISHENG , WU KENONG , PARK ALLEN , CHANG ELLIS , ZAFAR KHURRAM , HUANG JUNQING JENNY , GU PING , MAHER CHRISTOPHER , CHEN GRACE H , RONG SONGNIAN , WU LIU-MING
IPC分类号： G06T7/60
CPC分类号： G06T7/001 , G06T2207/10061 , G06T2207/20021 , G06T2207/20056 , G06T2207/30148
摘要： The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.
摘要翻译：本发明包括搜索图像数据以便识别半导体晶片上的一个或多个图案化区域，生成一个或多个虚拟傅里叶滤波器（VFF）工作区域，从VFF工作区域获取初始图像数据集合，定义VFF训练使用初始图像数据集合在VFF工作区域的所识别图案化区域内的块，其中每个VFF训练块被定义为涵盖显示选定重复图案的所识别图案化区域的一部分，计算每个VFF训练块的初始光谱利用来自VFF训练块的初始图像数据集，并且通过识别在频域中具有最大值的初始频谱的频率来为每个训练块生成VFF，其中VFF被配置为使得初始频谱的幅度在确定频率显示频谱最大值。

6. 发明申请

WO2012016243A3 REGION BASED VIRTUAL FOURIER FILTER 审中-公开
标题翻译：基于区域的虚拟FOURIER过滤器
公开(公告)号：WO2012016243A3
公开(公告)日：2013-08-15
申请号：PCT/US2011046154
申请日：2011-08-01
申请人： KLA TENCOR CORP , GAO LISHENG , WU KENONG , PARK ALLEN , CHANG ELLIS , ZAFAR KHURRAM , HUANG JUNQING JENNY , GU PING , MAHER CHRISTOPHER , CHEN GRACE H , RONG SONGNIAN , WU LIU-MING
发明人： GAO LISHENG , WU KENONG , PARK ALLEN , CHANG ELLIS , ZAFAR KHURRAM , HUANG JUNQING JENNY , GU PING , MAHER CHRISTOPHER , CHEN GRACE H , RONG SONGNIAN , WU LIU-MING
IPC分类号： H01L21/66 , G06K9/00
CPC分类号： G06T7/001 , G06T2207/10061 , G06T2207/20021 , G06T2207/20056 , G06T2207/30148
摘要： The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.
摘要翻译：本发明包括搜索图像数据以便识别半导体晶片上的一个或多个图案化区域，生成一个或多个虚拟傅立叶滤波器（VFF）工作区域，从VFF工作区域获取初始图像数据集，定义VFF训练利用初始的图像数据集，在VFF工作区域的所识别的图案化区域内的块，其中每个VFF训练块被定义为包含所识别的图案化区域的一部分，显示所选择的重复模式，计算每个VFF训练块的初始频谱利用来自VFF训练块的初始图像数据组，以及通过识别在频域中具有最大值的初始频谱的频率，为每个训练块生成VFF，其中VFF被配置为在识别出显示频谱最大值的频率。

7. 发明申请

WO2011085255A3 INSPECTION GUIDED OVERLAY METROLOGY 审中-公开
标题翻译：检查指导覆盖度量
公开(公告)号：WO2011085255A3
公开(公告)日：2011-11-10
申请号：PCT/US2011020587
申请日：2011-01-07
申请人： KLA TENCOR CORP , CHANG ELLIS , WIDMANN AMIR , PARK ALLEN
发明人： CHANG ELLIS , WIDMANN AMIR , PARK ALLEN
IPC分类号： H01L21/66
CPC分类号： G01N21/9501 , G01N21/95607 , G01N2021/8822 , G03F7/70633 , G03F7/7065 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.
摘要翻译：检查引导覆盖度量可以包括执行图案搜索以便识别半导体晶片上的预定图案，为半导体晶片上的预定图案的所有实例生成护理区域，通过执行检查扫描来检查所产生的护理区域内的缺陷每个生成的护理区域，其中检查扫描包括低阈值或高灵敏度检查扫描，识别具有大于使用缺陷检查技术的所选覆盖规格的测量覆盖误差的半导体晶片的预定图案的覆盖位置将生成的护理区域的所识别的缺陷的位置数据与生成的护理区域内的所识别的覆盖位置的位置数据进行比较，以便识别其中缺陷接近所识别的覆盖位置的一个或多个位置，以及生成计量取样基于确定的位置进行计划。

8. 发明申请

WO2012115912A3 DESIGN BASED DEVICE RISK ASSESSMENT 审中-公开
标题翻译：基于设计的设备风险评估
公开(公告)号：WO2012115912A3
公开(公告)日：2012-11-22
申请号：PCT/US2012025827
申请日：2012-02-20
申请人： KLA TENCOR CORP , PARK ALLEN , JIN YOUSEUNG , CHO SUNGCHAN , SAVILLE BARRY
发明人： PARK ALLEN , JIN YOUSEUNG , CHO SUNGCHAN , SAVILLE BARRY
IPC分类号： H01L21/00 , H01L21/66
CPC分类号： H01L22/12 , G01N21/95607 , G01N2021/8883 , G05B19/41875 , G05B2219/32182 , H01L22/20 , H01L2924/0002 , Y02P90/22 , Y02P90/265 , H01L2924/00
摘要： The present invention includes defining a multiple patterns of interest utilizing design data of the device; generating a design based classification database, the DBC database including design data associated with each of the POIs; receiving one or more inspection results; comparing the inspection results to each of the plurality of POIs in order to identify an occurrence of at least one of the POIs in the inspection results; determining yield impact of each POI utilizing process yield data; monitoring a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device; and determining a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons, the critical polygons defined utilizing design data of the device.
摘要翻译：本发明包括利用设备的设计数据来定义多个感兴趣的图案; 生成基于设计的分类数据库，所述DBC数据库包括与每个所述POI相关联的设计数据; 接收一个或多个检查结果; 将检查结果与多个POI中的每一个进行比较以便识别检查结果中的POI中的至少一个的发生; 利用过程产量数据确定每个POI的产量影响; 监测每个POI的出现频率和POI的临界程度，以便识别设备的过程偏移; 以及通过利用每个关键多边形的出现频率和每个关键多边形的关键性来计算该装置的归一化多边形频率来确定装置风险等级，该关键多边形利用该装置的设计数据来定义。

9. 发明申请

WO2007120279A3 METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA 审中-公开
标题翻译：与检验数据组合使用设计数据的方法和系统
公开(公告)号：WO2007120279A3
公开(公告)日：2008-11-20
申请号：PCT/US2006061112
申请日：2006-11-20
申请人： KLA TENCOR TECH CORP , ZAFAR KHURRAM , KEKARE SAGAR , CHANG ELLIS , PARK ALLEN , ROSE PETER
发明人： ZAFAR KHURRAM , KEKARE SAGAR , CHANG ELLIS , PARK ALLEN , ROSE PETER
IPC分类号： G06K9/00 , G06K9/62
CPC分类号： G01N21/9501 , G01N2021/8854 , G01R31/31718 , G06T7/001 , G06T2207/30148 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.
摘要翻译：提供了与检测数据结合使用设计数据的各种方法和系统。用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。此外，该方法包括将组中的缺陷合并，使得接近每个组中的缺陷位置的设计数据的部分至少相似。该方法还包括将合并步骤的结果存储在存储介质中。

10. 发明专利

SG192891A1 DESIGN BASED DEVICE RISK ASSESSMENT 未知
公开(公告)号：SG192891A1
公开(公告)日：2013-09-30
申请号：SG2013063565
申请日：2012-02-20
申请人： KLA TENCOR CORP
发明人： PARK ALLEN , JIN YOUSEUNG , CHO SUNGCHAN , SAVILLE BARRY
摘要： The present invention includes defining a multiple patterns of interest utilizing design data of the device; generating a design based classification database, the DBC database including design data associated with each of the POIs; receiving one or more inspection results; comparing the inspection results to each of the plurality of POIs in order to identify an occurrence of at least one of the POIs in the inspection results; determining yield impact of each POI utilizing process yield data; monitoring a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device; and determining a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons, the critical polygons defined utilizing design data of the device.

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