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1. 发明申请

US20090242989A1 COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR 审中-公开
标题翻译：具有嵌入式压力的补充金属氧化物半导体器件
公开(公告)号：US20090242989A1
公开(公告)日：2009-10-01
申请号：US12054933
申请日：2008-03-25
申请人： KEVIN K. CHAN , Jack O. Chu , Jin-Ping Han , Thomas S. Kanarsky , Hung Y. Ng , Qiqing Quyang , Gen Pei , Chun-Yung Sung , Henry K. Utomo , Thomas A. Wallner
发明人： KEVIN K. CHAN , Jack O. Chu , Jin-Ping Han , Thomas S. Kanarsky , Hung Y. Ng , Qiqing Quyang , Gen Pei , Chun-Yung Sung , Henry K. Utomo , Thomas A. Wallner
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78687 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66742 , H01L29/7848 , H01L29/78621
摘要： In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally from the gate electrode, where the stressor is formed of a silicon germanide alloy whose germanium content gradually increases in one direction.
摘要翻译：在一个实施例中，本发明是具有嵌入式应力源的互补金属氧化物半导体器件。场效应晶体管的一个实施例包括硅绝缘体沟道，耦合到绝缘体上硅沟道上的栅电极和嵌入在绝缘体上硅沟道中并与栅电极横向隔开的应力源，其中应力源由锗锗合金的锗含量在一个方向逐渐增加。

2. 发明申请

US20080083955A1 INTRINSICALLY STRESSED LINER AND FABRICATION METHODS THEREOF 审中-公开
标题翻译：本发明的内衬及其制造方法
公开(公告)号：US20080083955A1
公开(公告)日：2008-04-10
申请号：US11538506
申请日：2006-10-04
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/76829 , H01L21/76831 , H01L21/76841 , H01L21/76865 , H01L29/7843 , H01L29/7845
摘要： A stressed liner for improving carrier mobility in a transistor and a method for fabricating the same is disclosed. The stressed liner includes an intrinsically stressed conductive film encapsulated between two insulating layers such as silicon nitride, silicon oxide, or oxynitride. The stressed liner may be compressively-stressed or tensile-stressed depending on whether an n-FET or p-FET is required.
摘要翻译：公开了一种用于改善晶体管中的载流子迁移率的应力衬垫及其制造方法。应力衬里包括密封在两个绝缘层（例如氮化硅，氧化硅或氮氧化物）之间的本征应力导电膜。根据是否需要n-FET或p-FET，应力衬垫可以是压应力或拉伸应力。

3. 发明授权

US07989298B1 Transistor having V-shaped embedded stressor 有权
标题翻译：具有V形嵌入应力的晶体管
公开(公告)号：US07989298B1
公开(公告)日：2011-08-02
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

4. 发明申请

US20110183486A1 TRANSISTOR HAVING V-SHAPED EMBEDDED STRESSOR 有权
标题翻译：具有V形嵌入式应力的晶体管
公开(公告)号：US20110183486A1
公开(公告)日：2011-07-28
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

5. 发明授权

US07968915B2 Dual stress memorization technique for CMOS application 有权
标题翻译： CMOS应用的双重应力记忆技术
公开(公告)号：US07968915B2
公开(公告)日：2011-06-28
申请号：US12538110
申请日：2009-08-08
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

6. 发明申请

US20080303101A1 DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION 有权
标题翻译： CMOS应用的双应力记忆技术
公开(公告)号：US20080303101A1
公开(公告)日：2008-12-11
申请号：US11758291
申请日：2007-06-05
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed,
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中，

7. 发明授权

US06905941B2 Structure and method to fabricate ultra-thin Si channel devices 失效
标题翻译：制造超薄Si通道器件的结构和方法
公开(公告)号：US06905941B2
公开(公告)日：2005-06-14
申请号：US10250069
申请日：2003-06-02
申请人： Bruce B. Doris , Thomas S. Kanarsky , Meikei Ieong , Wesley C. Natzle
发明人： Bruce B. Doris , Thomas S. Kanarsky , Meikei Ieong , Wesley C. Natzle
IPC分类号： H01L21/762 , H01L21/84 , H01L21/76
CPC分类号： H01L21/84 , H01L21/76283
摘要： A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.
摘要翻译：提供了一种用于防止在隔离的超薄Si沟道器件的有源器件区域下形成多晶硅的方法。该方法使用化学氧化物去除（COR）处理步骤来防止托管架形成，而不是采用诸如HF的化学蚀刻剂的常规湿法蚀刻工艺。还提供了绝缘体上硅（SOI）结构。该结构包括至少位于掩埋绝缘层上的顶部含Si层; 以及位于顶部含Si层和掩埋绝缘层的一部分中的氧化物填充沟槽隔离区。顶部含Si层下方没有底切区域。

8. 发明授权

US06677646B2 Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS 有权
标题翻译：用于高性能凹槽通道CMOS的一次性反向间隔器工艺的方法和结构
公开(公告)号：US06677646B2
公开(公告)日：2004-01-13
申请号：US10117959
申请日：2002-04-05
申请人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
发明人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/456 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.
摘要翻译：一种高性能凹陷沟道CMOS器件，包括具有凹陷沟道区域和相邻的延伸注入区域和可选的晕轮植入区域的SOI层; 并且提供存在于SOI层顶上的至少一个栅极区域及其制造方法。邻接的延伸部分和可选的晕轮植入区域具有突然的侧向轮廓并且位于所述栅极区域下方。

9. 发明授权

US07834399B2 Dual stress memorization technique for CMOS application 有权
标题翻译： CMOS应用的双重应力记忆技术
公开(公告)号：US07834399B2
公开(公告)日：2010-11-16
申请号：US11758291
申请日：2007-06-05
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

10. 发明授权

US07314789B2 Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification 有权
标题翻译：用于产生MOSFET通道迁移率修正的局部机械栅极应力的结构和方法
公开(公告)号：US07314789B2
公开(公告)日：2008-01-01
申请号：US11618751
申请日：2006-12-30
申请人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
发明人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/04
CPC分类号： H01L29/7845 , H01L21/3215 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.
摘要翻译：提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

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