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1. 发明授权

US07256092B2 Method for fabricating integrated circuits having both high voltage and low voltage devices 有权
标题翻译：用于制造具有高电压和低电压装置的集成电路的方法
公开(公告)号：US07256092B2
公开(公告)日：2007-08-14
申请号：US10710616
申请日：2004-07-25
申请人： Jung-Ching Chen , Jy-Hwang Lin , Sheng-Hsiung Yang , Jim Su
发明人： Jung-Ching Chen , Jy-Hwang Lin , Sheng-Hsiung Yang , Jim Su
IPC分类号： H01L21/8232
CPC分类号： H01L29/1083 , H01L21/2652 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/823892 , H01L29/7833
摘要： A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.
摘要翻译：提供了与低压MOS工艺完全兼容的高压半导体MOS工艺。在定义有源区之前，将高压N / P阱注入到衬底中。在形成场氧化物层之后形成通道停止掺杂区域，从而避免沟道停止掺杂区域的横向扩散。此外，用于激活高压器件区域中的等级掺杂区域和高压器件的栅极氧化物生长的等级驱入工艺同时进行。

2. 发明授权

US6150916A Architecture of poly fuses 有权
标题翻译：保险丝架构
公开(公告)号：US6150916A
公开(公告)日：2000-11-21
申请号：US149929
申请日：1998-09-09
申请人： Jy-Hwang Lin , Tsan-Wen Liu
发明人： Jy-Hwang Lin , Tsan-Wen Liu
IPC分类号： H01L23/525 , H01L27/108 , H01H37/36 , H01L27/10 , H01L27/115
CPC分类号： H01L23/5258 , H01L27/10897 , H01L2924/0002
摘要： An architecture of poly fuses includes a number of fuses, a dielectric layer, a sheet-like etching stop layer, and a passivation layer, wherein the sheet-like etching stop layer further includes a number of slices, and wherein each of the slices corresponds to one of the fuses underneath. The architecture of poly fuses according to the invention reduces the energy dispersion during the defective recovering process, and improves the recovery rate for defective memory cells.
摘要翻译：多熔丝的结构包括多个保险丝，电介质层，片状蚀刻停止层和钝化层，其中片状蚀刻停止层还包括多个片，并且其中每个片对应于到下面的保险丝之一。根据本发明的多熔丝的结构降低了在有缺陷的恢复过程中的能量分散，并提高了有缺陷的存储单元的恢复率。

3. 发明授权

US07091079B2 Method of forming devices having three different operation voltages 有权
标题翻译：形成具有三种不同工作电压的器件的方法
公开(公告)号：US07091079B2
公开(公告)日：2006-08-15
申请号：US10904455
申请日：2004-11-11
申请人： Jung-Ching Chen , Jy-Hwang Lin
发明人： Jung-Ching Chen , Jy-Hwang Lin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/823892
摘要： The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a plurality of n-wells and a plurality of p-wells are in the HV region, the MV region, and the LV region. Following that, a plurality of HV devices are formed in the HV region, a plurality of MV devices are formed in the MV region, and a plurality of LV devices are formed in the LV region.
摘要翻译：本发明提供一种形成具有不同工作电压的器件的方法。首先，提供具有HV区域，MV区域和LV区域的基板。然后，在衬底中形成至少包围LV区域和MV区域的深阱。之后，多个n阱和多个p阱位于HV区域，MV区域和LV区域中。接着，在HV区域形成多个HV器件，在MV区域形成多个MV器件，在LV区域形成多个LV器件。

4. 发明申请

US20060099753A1 METHOD OF FORMING DEVICES HAVING THREE DIFFERENT OPERATION VOLTAGES 有权
标题翻译：形成具有三种不同操作电压的装置的方法
公开(公告)号：US20060099753A1
公开(公告)日：2006-05-11
申请号：US10904455
申请日：2004-11-11
申请人： Jung-Ching CHEN , Jy-Hwang Lin
发明人： Jung-Ching CHEN , Jy-Hwang Lin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/823892
摘要： The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a plurality of n-wells and a plurality of p-wells are in the HV region, the MV region, and the LV region. Following that, a plurality of HV devices are formed in the HV region, a plurality of MV devices are formed in the MV region, and a plurality of LV devices are formed in the LV region.
摘要翻译：本发明提供一种形成具有不同工作电压的器件的方法。首先，提供具有HV区域，MV区域和LV区域的基板。然后，在衬底中形成至少包围LV区域和MV区域的深阱。之后，多个n阱和多个p阱位于HV区域，MV区域和LV区域中。接着，在HV区域形成多个HV器件，在MV区域形成多个MV器件，在LV区域形成多个LV器件。

5. 发明授权

US6165895A Fabrication method of an interconnect 失效
标题翻译：互连的制造方法
公开(公告)号：US6165895A
公开(公告)日：2000-12-26
申请号：US344865
申请日：1999-06-28
申请人： Jy-Hwang Lin
发明人： Jy-Hwang Lin
IPC分类号： H01L21/027 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76885 , H01L21/0276 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76897
摘要： A method of fabricating an interconnect is described in which a conductive layer, an anti-reflection layer and a cover layer are sequentially formed on the substrate to form a conductive plug with its bottom situated in the anti-reflection layer. The cover layer and a portion of the anti-reflection layer and the conductive layer are remove to form an opening exposing the substrate and to define the conductive lining structures. A conformal polysilicon oxide layer is formed on the substrate and a first dielectric layer is also formed, filling the opening. A conformal isolation layer is then formed on the substrate, followed by forming a second dielectric layer covering the entire substrate. A planarization procedure is further conducted to expose the conductive plug.
摘要翻译：描述了制造互连的方法，其中在衬底上依次形成导电层，抗反射层和覆盖层，以形成其底部位于抗反射层中的导电插塞。去除覆盖层和防反射层和导电层的一部分以形成露出衬底并限定导电衬里结构的开口。在基板上形成保形多晶硅氧化物层，并且还形成填充开口的第一介电层。然后在衬底上形成保形隔离层，随后形成覆盖整个衬底的第二介电层。进一步进行平面化处理以暴露导电插塞。

6. 发明申请

US20060017114A1 METHOD FOR FABRICATING INTEGRATED CIRCUITS HAVING BOTH HIGH VOLTAGE AND LOW VOLTAGE DEVICES 有权
标题翻译：用于制造具有两个高电压和低电压装置的集成电路的方法
公开(公告)号：US20060017114A1
公开(公告)日：2006-01-26
申请号：US10710616
申请日：2004-07-25
申请人： Jung-Ching Chen , Jy-Hwang Lin , Sheng-Hsiung Yang , Jim SU
发明人： Jung-Ching Chen , Jy-Hwang Lin , Sheng-Hsiung Yang , Jim SU
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/1083 , H01L21/2652 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/823892 , H01L29/7833
摘要： A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.
摘要翻译：提供了与低压MOS工艺完全兼容的高压半导体MOS工艺。在定义有源区之前，将高压N / P阱注入到衬底中。在形成场氧化物层之后形成通道停止掺杂区域，从而避免沟道停止掺杂区域的横向扩散。此外，用于激活高压器件区域中的等级掺杂区域和高压器件的栅极氧化物生长的等级驱入工艺同时进行。

7. 发明授权

US6133143A Method of manufacturing interconnect 有权
标题翻译：制造互连的方法
公开(公告)号：US6133143A
公开(公告)日：2000-10-17
申请号：US340928
申请日：1999-06-28
申请人： Jy-Hwang Lin , Ching-Hsing Hsieh , Yueh-Feng Ho , Chia-Chieh Yu
发明人： Jy-Hwang Lin , Ching-Hsing Hsieh , Yueh-Feng Ho , Chia-Chieh Yu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/31133 , H01L21/76802 , H01L21/76814 , H01L21/76877
摘要： The invention provides a method of manufacturing a metal interconnect. A substrate having a metal line formed thereon is provided. An anti-reflection layer is formed on the metal line. A dielectric layer with a relatively low dielectric constant is formed over the substrate. A patterned photoresist layer is formed on the dielectric layer. The patterned photoresist layer has an opening exposing a portion of the dielectric layer. The portion of the dielectric layer exposed by the opening is removed to form a via hole. The patterned photoresist layer is removed by an O.sub.2 --H.sub.2 O--CF.sub.4 plasma. The pressure of the O.sub.2 --H.sub.2 O--CF.sub.4 plasma is about 800-1000 torr. A cleaning process is performed by a post-stripper rinse solution and de-ionized water without using an acetone solution. A barrier layer is formed over the substrate by chemical vapor deposition. A metal nucleation is performed for a long time by chemical vapor deposition to form metal nuclei on the barrier layer. A metal layer is formed to fill the via hole by chemical vapor deposition.
摘要翻译：本发明提供一种制造金属互连的方法。提供其上形成有金属线的基板。在金属线上形成防反射层。在衬底上形成介电常数较低的电介质层。在电介质层上形成图案化的光致抗蚀剂层。图案化的光致抗蚀剂层具有露出电介质层的一部分的开口。通过开口暴露的电介质层的部分被去除以形成通孔。通过O 2 -H 2 O-CF 4等离子体去除图案化的光致抗蚀剂层。 O2-H2O-CF4等离子体的压力约为800-1000乇。在不使用丙酮溶液的情况下，通过脱胶器冲洗溶液和去离子水进行清洁处理。通过化学气相沉积在衬底上形成阻挡层。通过化学气相沉积长时间进行金属成核，以在阻挡层上形成金属核。形成金属层以通过化学气相沉积填充通孔。

8. 再颁专利

USRE44156E1 Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage 有权
标题翻译：用于在具有高/低压环境的环境中操作的单级电可擦除和可编程只读存储器的形成方法
公开(公告)号：USRE44156E1
公开(公告)日：2013-04-16
申请号：US11391667
申请日：2006-03-29
申请人： Rong-Ching Chen , Ching-Chun Huang , Jy-Hwang Lin
发明人： Rong-Ching Chen , Ching-Chun Huang , Jy-Hwang Lin
IPC分类号： H01L21/02 , H01L21/336
CPC分类号： H01L27/11526 , G11C16/10 , H01L27/115 , H01L27/11546
摘要： First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.
摘要翻译：首先，提供半导体衬底，然后在其中形成具有第一导电性的第一/第二阱，以分别形成单电平EEPROM的浮置栅极的第一部分和其上的低压器件，其中第一井和第二井用于分离高压装置，第一井的深度与第二井相同。此外，单电平EEPROM的高压器件和浮置栅极的第二部分分别形成在第一和第二阱之间的半导体衬底上，并且形成单级EEPROM的浮置栅极的控制栅极位于单电平EEPROM的浮置栅极的第二部分下方的第三阱中，其中高电压装置可以在大约18V的相对电场中操作，例如-6V〜12V，-12V〜6V，-9V 〜9V等

9. 发明申请

US20050130378A1 METHOD OF INTEGRATING HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR DEVICES AND SUBMICRON METAL OXIDE SEMICONDUCTOR DEVICES 有权
标题翻译：集成高电压金属氧化物半导体器件和次级金属氧化物半导体器件的方法
公开(公告)号：US20050130378A1
公开(公告)日：2005-06-16
申请号：US10707444
申请日：2003-12-15
申请人： Ching-Chun Huang , Ming-Hsien Huang , Rong-Ching Chen , Jy-Hwang Lin
发明人： Ching-Chun Huang , Ming-Hsien Huang , Rong-Ching Chen , Jy-Hwang Lin
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/336 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/823418 , H01L21/823456
摘要： The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.
摘要翻译：本发明提供一种将至少一个高电压金属氧化物半导体器件和至少一个亚微米金属氧化物半导体器件集成在衬底上的方法。该方法包括：提供衬底，在衬底的表面上形成具有不同深度的多个浅沟槽，以及形成填充浅沟槽的多个氧化硅层，并且每个氧化硅层的顶部处于蘑菇的形状。

10. 发明授权

US6083825A Method of forming unlanded via hole 有权
标题翻译：无凹陷通孔的形成方法
公开(公告)号：US6083825A
公开(公告)日：2000-07-04
申请号：US329113
申请日：1999-06-09
申请人： Jy-Hwang Lin , Yueh-Feng Ho , Pei-Jen Wang
发明人： Jy-Hwang Lin , Yueh-Feng Ho , Pei-Jen Wang
IPC分类号： H01L21/3213 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/32139
摘要： An improved method of fabricating an unlanded via hole on a semiconductor substrate is provided. A conductive line and a patterned anti-reflection coating layer are sequentially formed on the substrate wherein the patterned anti-reflection coating layer has a smaller width than the conductive line and a portion of the conductive layer is exposed by the patterned anti-reflection coating layer. A planarized dielectric layer is formed over the substrate to cover the patterned anti-reflection coating layer and the conductive line. A via hole is formed in the planarized dielectric layer to expose portions of surface and sidewalls of the patterned anti-reflection coating layer as well as the conductive line.
摘要翻译：提供了一种在半导体衬底上制造无衬底通孔的改进方法。在基板上依次形成导电线和图案化的抗反射涂层，其中图案化的抗反射涂层具有比导电线更小的宽度，并且导电层的一部分被图案化的抗反射涂层。平面化介电层形成在衬底上以覆盖图案化的抗反射涂层和导线。在平坦化的电介质层中形成通孔以暴露图案化的抗反射涂层以及导电线的表面和侧壁的部分。

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