专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100153626A1 MEMORY SYSTEM 失效
标题翻译：记忆系统
公开(公告)号：US20100153626A1
公开(公告)日：2010-06-17
申请号：US12529223
申请日：2009-02-10
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Hiroki Matsudaira
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda , Hiroki Matsudaira
IPC分类号： G06F12/00 , G06F12/16 , G06F12/02
CPC分类号： G06F11/1435 , G06F11/1441 , G06F11/1471 , G06F11/1474
摘要： To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.
摘要翻译：提供即使在数据写入过程中发生程序错误时也可以确保还原管理信息的存储系统。在“日志写入（1）”作为预登录之后，当执行数据写入时发生程序错误（数据写入错误）时，存储器系统再次执行数据写入，而不获取对应于数据重写的预记录处理。在完成数据写入之后，内存系统在不生成后记录的情况下获取快照而不是后记录，并完成处理。

2. 发明授权

US08171208B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US08171208B2
公开(公告)日：2012-05-01
申请号：US12529126
申请日：2009-02-10
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F11/1068 , G06F12/0246 , G06F12/0804 , G06F2212/1032 , G06F2212/2022 , G06F2212/7203
摘要： A memory system includes a DRAM 20 that performs writing and readout in a unit equal to or smaller than a cluster, a NAND memory 10 that performs writing and readout in a page unit, and a management table group in which management information including storage locations of data stored in the DRAM 20 and the NAND memory 10 is stored. When a readout request is received from the outside, a data managing unit 120 notifies, when an unwritten logical address area is present in a storage area of the NAND memory to which a logical address area requested to be read out is mapped, fixed data stored in the DRAM 20 to the outside in association with the logical address area.
摘要翻译：存储器系统包括以等于或小于簇的单位执行写入和读出的DRAM 20，以页单元执行写入和读出的NAND存储器10以及管理表组，其中管理信息包括存储位置存储在DRAM 20和NAND存储器10中的数据被存储。当从外部接收到读出请求时，数据管理单元120在映射了要求读出的逻辑地址区域的NAND存储器的存储区域中存在未写入的逻辑地址区域时，通知存储的固定数据在DRAM 20中与逻辑地址区域相关联到外部。

3. 发明申请

US20110185108A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20110185108A1
公开(公告)日：2011-07-28
申请号：US12529235
申请日：2009-02-10
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F12/00 , G06F12/16
CPC分类号： G11C16/102 , G06F11/141 , G06F11/1443 , G06F11/1471 , G11C11/5628 , G11C16/0483 , G11C16/105 , G11C29/00
摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data.
摘要翻译：存储器系统包括易失性第一存储单元，非易失性第二存储单元，其中排列可存储多值数据的多个存储器单元，存储单元具有多个页面，以及控制器，其执行数据传输主机设备和第二存储单元。控制器包括一个保存处理单元，其在一次写入数据被写入第二存储单元之后，当数据被写入到存储单元的低位页面中时写入数据，低位页的数据和破损信息恢复处理单元，当低位页中的数据被破坏时，使用备份数据恢复断开的数据。

4. 发明授权

US07904640B2 Memory system with write coalescing 失效
标题翻译：具有写入合并的内存系统
公开(公告)号：US07904640B2
公开(公告)日：2011-03-08
申请号：US12529270
申请日：2008-09-22
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1016 , G06F2212/7203 , G06F2212/7205
摘要： A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.
摘要翻译：控制器执行用于在第一存储区域中以扇区为单位写入多个数据的第一处理; 第二处理，用于将存储在第一存储区域中的数据在第一管理单元中的第一输入缓冲器中刷新自然数倍于扇区单元的两倍或更大; 在第二管理单元中将存储在第一存储区域中的数据刷新到与第一管理单元一样大的自然数倍的两倍或更大的第二处理; 将其中将所有页面写入所述第一输入缓冲器的逻辑块重定位到所述第二存储区域的第四处理; 将其中将所有页面写入第二输入缓冲器的逻辑块重新定位到第三存储区域的第五处理; 以及第六处理，用于将存储在第二存储区域中的多个数据刷新到第二管理单元中的第二输入缓冲器。

5. 发明申请

US20110022784A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20110022784A1
公开(公告)日：2011-01-27
申请号：US12529139
申请日：2009-02-10
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Toshikatsu Hida
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Toshikatsu Hida
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7207 , G06F2212/7208 , G06F2212/7211
摘要： A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.
摘要翻译：根据本发明的实施例的存储器系统包括：通过采用包括分别具有多个物理块的多个并行操作元件作为数据擦除单元的非易失性半导体存储器来减少管理表创建所需的存储量，并且控制器，其可以并行驱动并行操作元件，并且具有多个次数的擦除管理单元，其管理与并行驱动的多个物理块相关联的逻辑块单元中的擦除次数。

6. 发明申请

US20100281204A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20100281204A1
公开(公告)日：2010-11-04
申请号：US12529193
申请日：2008-09-22
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F12/0897 , G06F2212/1016 , G06F2212/7203
摘要： A memory system includes a WC 21 from which data is read out and to which data is written in sector units by a host apparatus, an FS 12 from which data is read out and to which data is written in page units, an MS 11 from which data is read out and to which data written in track units, an FSIB 12a functioning as an input buffer for the FS 12, and an MSIB 11a functioning as an input buffer to the MS 11. An FSBB 12ac that has a capacity equal to or larger than a storage capacity of the WC 21 and stores data written in the WC 21 is provided in the FSIB12a. A data managing unit 120 that manages the respective storing units suspends, when it is judged that one kind of processing performed among the storing units exceeds predetermined time, the processing judged as exceeding the predetermined time and controls the data written in the WC 21 to be saved in the FSBB 12ac.
摘要翻译：存储器系统包括从其读出数据并由主机设备以扇区单元写入数据的WC 21，读出数据并以页为单位写入数据的FS12，MS11从MS 读出哪个数据，以轨道单位写入哪个数据，用作FS12的输入缓冲器的FSIB 12a和用作MS 11的输入缓冲器的MSIB 11a。具有等于或大于WC 21的存储容量并且存储写入WC 21的数据被提供在FSIB12a中。管理各个存储单元的数据管理单元120当判定存储单元之间执行的一种处理超过预定时间时，判断为超过预定时间的处理，并且将写入WC 21中的数据控制为保存在FSBB 12ac中。

7. 发明申请

US20090248964A1 MEMORY SYSTEM AND METHOD FOR CONTROLLING A NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：用于控制非易失性半导体存储器的存储器系统和方法
公开(公告)号：US20090248964A1
公开(公告)日：2009-10-01
申请号：US12394632
申请日：2009-02-27
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Wataru Okamoto
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Wataru Okamoto
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F3/061 , G06F3/065 , G06F3/0661 , G06F3/0679 , G06F12/0246 , G06F2206/1014 , G06F2212/7203 , G06F2212/7205 , G11C11/5628 , G11C16/0483 , G11C16/102 , G11C2211/5643 , G11C2211/5646
摘要： A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management tablet the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.
摘要翻译：存储器系统包括具有块的非易失性半导体存储器，该块是数据擦除单元; 以及控制器，被配置为执行; 更新处理; 在块中写入替代数据，替代数据被视为有效数据; 并且使具有与取代数据相同的逻辑地址的替代数据无效，所取代的数据被视为无效数据; 和压实处理; 使用管理数据库检索具有无效数据的块，所述管理表管理所述块中包括的每个数量的有效数据的链接列表格式的块; 从所检索的块中选择具有至少一个有效数据的压缩源块; 将压缩源块中包括的多个有效数据复制到压缩目标块中; 使压缩源块中的多个有效数据无效; 并释放其中所有数据无效的压缩源块。

8. 发明申请

US20090228642A1 MEMORY SYSTEM AND DATA ERASING METHOD THEREFOR 失效
标题翻译：存储系统和数据擦除方法
公开(公告)号：US20090228642A1
公开(公告)日：2009-09-10
申请号：US12394720
申请日：2009-02-27
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7205 , G06F2212/7207
摘要： A memory system includes a management table group in which management information including storage positions of data stored in a first storing area and a second storing area is stored. The management table group is stored in the second storing area. A controller performs data transfer between a host apparatus and the second storing area via the first storing area and performs management of the data in the first and second storing areas based on the management table group while updating the management table group expanded in the first storing area. The second storing area can store data associated with a first logical address area accessible from the host apparatus and data associated with a second logical address area accessible from the host apparatus, and the controller receives an erasing command from the host apparatus, collects the data associated with the second logical address area in a predetermined area in the second storing area, and then initializes the management table group.
摘要翻译：存储器系统包括管理表组，其中存储包括存储在第一存储区域和第二存储区域中的数据的存储位置的管理信息。管理表组存储在第二存储区域中。控制器经由第一存储区域在主机设备和第二存储区域之间执行数据传送，并且在更新在第一存储区域中扩展的管理表组的同时，基于管理表组来执行第一和第二存储区域中的数据的管理。第二存储区域可以存储与从主机设备可访问的第一逻辑地址区域相关联的数据和与从主机设备可访问的第二逻辑地址区域相关联的数据，并且控制器从主机设备接收擦除命令，收集相关联的数据第二逻辑地址区域在第二存储区域中的预定区域中，然后初始化管理表组。

9. 发明授权

US08745313B2 Memory system and method for controlling a nonvolatile semiconductor memory 有权
标题翻译：用于控制非易失性半导体存储器的存储器系统和方法
公开(公告)号：US08745313B2
公开(公告)日：2014-06-03
申请号：US12394632
申请日：2009-02-27
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Wataru Okamoto
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki , Wataru Okamoto
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/065 , G06F3/0661 , G06F3/0679 , G06F12/0246 , G06F2206/1014 , G06F2212/7203 , G06F2212/7205 , G11C11/5628 , G11C16/0483 , G11C16/102 , G11C2211/5643 , G11C2211/5646
摘要： A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management tablet the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.
摘要翻译：存储器系统包括具有块的非易失性半导体存储器，该块是数据擦除单元; 以及控制器，被配置为执行; 更新处理; 在块中写入替代数据，替代数据被视为有效数据; 并且使具有与取代数据相同的逻辑地址的替代数据无效，所取代的数据被视为无效数据; 和压实处理; 使用管理数据库检索具有无效数据的块，所述管理表管理所述块中包括的每个数量的有效数据的链接列表格式的块; 从所检索的块中选择具有至少一个有效数据的压缩源块; 将压缩源块中包括的多个有效数据复制到压缩目标块中; 使压缩源块中的多个有效数据无效; 并释放其中所有数据无效的压缩源块。

10. 发明授权

US08554984B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US08554984B2
公开(公告)日：2013-10-08
申请号：US12529127
申请日：2009-02-10
申请人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki
发明人： Junji Yano , Kosuke Hatsuda , Hidenori Matsuzaki
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F2212/1016 , G06F2212/1044 , G06F2212/1048 , G06F2212/7201 , G06F2212/7209
摘要： A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked.
摘要翻译：通过提供从逻辑地址，数据对应于逻辑地址的存储设备位置分别在轨道和群集单元中搜索的前向查找表来增加用于通过管理表搜索的处理速度的存储器系统，以及用于从存储设备的位置搜索存储在该位置中的逻辑地址的反向查找表。这些正向和反向查找表是链接的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式