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1. 发明申请

US20060022325A1 Cap wafer, semiconductor package, and fabricating method thereof 审中-公开
标题翻译：封装晶片，半导体封装及其制造方法
公开(公告)号：US20060022325A1
公开(公告)日：2006-02-02
申请号：US11189725
申请日：2005-07-27
申请人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , In-sang Song
发明人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , In-sang Song
IPC分类号： H01L23/544
CPC分类号： B81B7/007 , H01L23/04 , H01L2224/48463 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/16235 , H01L2924/00015 , H01L2924/00
摘要： A cap wafer including a cavity, a packaged semiconductor including the cap wafer, and a method of fabricating the cap wafer. The cap wafer includes a cavity formed in an area of a lower surface of the cap wafer; and at least one feed-through penetrating through upper and lower surfaces of the cap wafer so as to be connected to the cavity. The packaged semiconductor includes a base wafer including an upper surface including an area in which a circuit device is formed; a cap wafer including a lower surface including an area in which a cavity having a predetermined size is formed, the cap wafer being combined with the base wafer to position the circuit device in the cavity so as to package the circuit device; and at least one feed-through penetrating through upper and lower portions of the cap wafer so as to be connected to the cavity and electrically connected to the circuit device.
摘要翻译：包括空腔的盖晶片，包括盖晶片的封装半导体以及制造盖晶片的方法。盖晶片包括形成在盖晶片的下表面的区域中的空腔; 以及至少一个穿透帽盖晶片的上表面和下表面的馈通以连接到腔体。封装半导体包括：基底晶片，其包括具有形成电路器件的区域的上表面; 包括具有形成具有预定尺寸的空腔的下表面的盖晶片，所述盖晶片与所述基底晶片组合以将所述电路器件定位在所述腔中以封装所述电路器件; 以及至少一个穿透帽盖晶片的上部和下部的馈通，以便连接到腔并电连接到电路装置。

2. 发明授权

US07755151B2 Wafer level package for surface acoustic wave device and fabrication method thereof 有权
标题翻译：用于表面声波器件的晶片级封装及其制造方法
公开(公告)号：US07755151B2
公开(公告)日：2010-07-13
申请号：US11415099
申请日：2006-05-02
申请人： Ji-hyuk Lim , Jun-sik Hwang , Woon-bae Kim , Suk-jin Ham , Jong-oh Kwon , Moon-chul Lee , Chang-youl Moon
发明人： Ji-hyuk Lim , Jun-sik Hwang , Woon-bae Kim , Suk-jin Ham , Jong-oh Kwon , Moon-chul Lee , Chang-youl Moon
IPC分类号： H01L29/82 , H01L23/04 , H01L21/00
CPC分类号： H03H9/1092
摘要： A wafer level package for a surface acoustic wave device and a fabrication method thereof include a SAW device formed with a SAW element on an upper surface of a device wafer; a cap wafer joined on an upper part of the SAW element; a cavity part housing the SAW element between the cap wafer and the SAW device; a cap pad formed on an upper surface of the cap wafer; and a metal line formed to penetrate through the cap wafer to electrically connect the cap pad and the SAW element, the device wafer and the cap wafer being made of the same materials.
摘要翻译：用于声表面波器件的晶片级封装及其制造方法包括在器件晶片的上表面上形成有SAW元件的SAW器件; 接合在所述SAW元件的上部的盖晶片; 在所述盖晶片和所述SAW器件之间容纳所述SAW元件的空腔部; 帽盖，形成在盖晶片的上表面上; 以及金属线，其形成为穿透盖晶片以电连接帽垫和SAW元件，器件晶片和盖晶片由相同的材料制成。

3. 发明授权

US07335974B2 Multi stack packaging chip and method of manufacturing the same 有权
标题翻译：多堆叠封装芯片及其制造方法相同
公开(公告)号：US07335974B2
公开(公告)日：2008-02-26
申请号：US11391211
申请日：2006-03-29
申请人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
发明人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： B81C1/0023 , B81B7/007 , B81C2203/0118 , H01L23/04 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/48463 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/16235 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.
摘要翻译：提供了一种多层封装芯片及其制造方法。该方法包括在第一晶片上形成至少一个第二电路元件; 形成具有空腔的第二晶片和与所述腔相对形成的一个第三电路元件; 在第二晶片上形成焊料; 以及将所述第二晶片与所述第一晶片组合以使得所述第二电路元件和所述空腔对应。芯片包括倒装芯片封装芯片，其中使用第一晶片封装第一电路元件; 形成在第一晶片上的第二电路元件; 第二晶片，其具有空腔并与所述第一晶片组合，使得所述空腔和所述第二电路元件对应; 形成在第二晶片上的第三电路元件; 以及形成在所述第二晶片上的焊料，所述焊料将所述第二晶片电耦合到封装衬底。

4. 发明授权

US07449366B2 Wafer level packaging cap and fabrication method thereof 有权
标题翻译：晶圆级封装盖及其制造方法
公开(公告)号：US07449366B2
公开(公告)日：2008-11-11
申请号：US11365838
申请日：2006-03-02
申请人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Ji-hyuk Lim , Suk-jin Ham , Jun-sik Hwang , Chang-youl Moon
发明人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Ji-hyuk Lim , Suk-jin Ham , Jun-sik Hwang , Chang-youl Moon
IPC分类号： H01L21/00
CPC分类号： B81C1/00301 , B81B2207/095 , H01L21/4817 , H01L21/50 , H01L2924/16235
摘要： A wafer level packaging cap for covering a device wafer with a device thereon and a fabrication method thereof are provided. The method includes operations of forming a plurality of connection grooves on a wafer, forming a seed layer on the connection grooves, forming connection parts by filling the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the top surface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to the connection parts.
摘要翻译：提供了一种用于在其上覆盖器件晶片的晶片级封装盖及其制造方法。该方法包括在晶片上形成多个连接槽的操作，在连接槽上形成种子层，通过用金属材料填充连接槽来形成连接部分，在晶片的顶表面上形成电极盖连接到连接部分，将支撑膜与其上形成有盖垫的晶片的顶表面接合，在晶片的底表面上形成空腔，以通过空腔露出连接部分，并在其上形成金属线晶片的底表面电连接到连接部分。

5. 发明申请

US20060255443A1 Multi stack packaging chip and method of manufacturing the same 有权
标题翻译：多堆叠封装芯片及其制造方法相同
公开(公告)号：US20060255443A1
公开(公告)日：2006-11-16
申请号：US11391211
申请日：2006-03-29
申请人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
发明人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
IPC分类号： H01L23/02
CPC分类号： B81C1/0023 , B81B7/007 , B81C2203/0118 , H01L23/04 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/48463 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/16235 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.
摘要翻译：提供了一种多层封装芯片及其制造方法。该方法包括在第一晶片上形成至少一个第二电路元件; 形成具有空腔的第二晶片和与所述腔相对形成的一个第三电路元件; 在第二晶片上形成焊料; 以及将所述第二晶片与所述第一晶片组合以使得所述第二电路元件和所述空腔对应。芯片包括倒装芯片封装芯片，其中使用第一晶片封装第一电路元件; 形成在第一晶片上的第二电路元件; 第二晶片，其具有空腔并与所述第一晶片组合，使得所述空腔和所述第二电路元件对应; 形成在第二晶片上的第三电路元件; 以及形成在所述第二晶片上的焊料，所述焊料将所述第二晶片电耦合到封装衬底。

6. 发明授权

US07452809B2 Fabrication method of packaging substrate and packaging method using the packaging substrate 有权
标题翻译：包装基材的包装方法和封装方法
公开(公告)号：US07452809B2
公开(公告)日：2008-11-18
申请号：US11240771
申请日：2005-10-03
申请人： Moon-chul Lee , Woon-bae Kim , Jun-sik Hwang , Chang-youl Moon
发明人： Moon-chul Lee , Woon-bae Kim , Jun-sik Hwang , Chang-youl Moon
IPC分类号： H01L21/44 , H01R43/00
CPC分类号： B81C1/00301 , Y10T29/49117
摘要： A fabrication method of a packaging substrate includes the steps of: forming a recess by etching a predetermined area of a lower surface of a substrate; depositing a seed layer on an upper surface of the substrate; in the recess, etching predetermined area(s) of the lower surface of the substrate and forming at least one via hole that reaches the seed layer; and plating the inside of the via hole by using the seed layer, and forming electrode(s) for electrically coupling the upper and lower parts of the substrate. First and second pads coupled to the electrode(s) may be formed on the upper and lower parts of the substrate, respectively. Thus, using the second pads as bonding materials, the packaging process becomes easier, which resultantly simplifies the fabrication process of the packaging substrate and the packaging process.
摘要翻译：包装基板的制造方法包括以下步骤：通过蚀刻基板的下表面的预定区域来形成凹部; 在基板的上表面上沉积种子层; 在所述凹部中蚀刻所述基板的下表面的预定区域并形成到达所述籽晶层的至少一个通孔; 并且通过使用晶种层对通孔的内部进行电镀，以及形成用于电耦合衬底的上部和下部的电极。分别连接到电极的第一和第二焊盘分别形成在衬底的上部和下部。因此，使用第二焊盘作为粘合材料，封装过程变得更容易，从而简化了封装衬底的制造过程和封装过程。

7. 发明申请

US20060094158A1 Fabrication method of packaging substrate and packaging method using the packaging substrate 有权
标题翻译：包装基材的包装方法和封装方法
公开(公告)号：US20060094158A1
公开(公告)日：2006-05-04
申请号：US11240771
申请日：2005-10-03
申请人： Moon-chul Lee , Woon-bae Kim , Jun-sik Hwang , Chang-youl Moon
发明人： Moon-chul Lee , Woon-bae Kim , Jun-sik Hwang , Chang-youl Moon
IPC分类号： H01L21/50
CPC分类号： B81C1/00301 , Y10T29/49117
摘要： A fabrication method of a packaging substrate includes the steps of: forming a recess by etching a predetermined area of a lower surface of a substrate; depositing a seed layer on an upper surface of the substrate; in the recess, etching predetermined area(s) of the lower surface of the substrate and forming at least one via hole that reaches the seed layer; and plating the inside of the via hole by using the seed layer, and forming electrode(s) for electrically coupling the upper and lower parts of the substrate. First and second pads coupled to the electrode(s) may be formed on the upper and lower parts of the substrate, respectively. Thus, using the second pads as bonding materials, the packaging process becomes easier, which resultantly simplifies the fabrication process of the packaging substrate and the packaging process.
摘要翻译：包装基板的制造方法包括以下步骤：通过蚀刻基板的下表面的预定区域来形成凹部; 在基板的上表面上沉积种子层; 在所述凹部中蚀刻所述基板的下表面的预定区域并形成到达所述籽晶层的至少一个通孔; 并且通过使用晶种层对通孔的内部进行电镀，以及形成用于电耦合衬底的上部和下部的电极。分别连接到电极的第一和第二焊盘分别形成在衬底的上部和下部。因此，使用第二焊盘作为粘合材料，封装过程变得更容易，从而简化了封装衬底的制造过程和封装过程。

8. 发明申请

US20070096227A1 Wafer level package for surface acoustic wave device and fabrication method thereof 有权
标题翻译：用于表面声波器件的晶片级封装及其制造方法
公开(公告)号：US20070096227A1
公开(公告)日：2007-05-03
申请号：US11415099
申请日：2006-05-02
申请人： Ji-hyuk Lim , Jun-sik Hwang , Woon-bae Kim , Suk-jin Ham , Jong-oh Kwon , Moon-chul Lee , Chang-youl Moon
发明人： Ji-hyuk Lim , Jun-sik Hwang , Woon-bae Kim , Suk-jin Ham , Jong-oh Kwon , Moon-chul Lee , Chang-youl Moon
IPC分类号： H01L29/84
CPC分类号： H03H9/1092
摘要： A wafer level package for a surface acoustic wave device and a fabrication method thereof include a SAW device formed with a SAW element on an upper surface of a device wafer; a cap wafer joined on an upper part of the SAW element; a cavity part housing the SAW element between the cap wafer and the SAW device; a cap pad formed on an upper surface of the cap wafer; and a metal line formed to penetrate through the cap wafer to electrically connect the cap pad and the SAW element, the device wafer and the cap wafer being made of the same materials.
摘要翻译：用于声表面波器件的晶片级封装及其制造方法包括在器件晶片的上表面上形成有SAW元件的SAW器件; 接合在所述SAW元件的上部的盖晶片; 在所述盖晶片和所述SAW器件之间容纳所述SAW元件的空腔部; 帽盖，形成在盖晶片的上表面上; 以及金属线，其形成为穿透盖晶片以电连接帽垫和SAW元件，器件晶片和盖晶片由相同的材料制成。

9. 发明申请

US20070085195A1 Wafer level packaging cap and fabrication method thereof 有权
标题翻译：晶圆级封装盖及其制造方法
公开(公告)号：US20070085195A1
公开(公告)日：2007-04-19
申请号：US11365838
申请日：2006-03-02
申请人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Ji-hyuk Lim , Suk-jin Ham , Jun-sik Hwang , Chang-youl Moon
发明人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Ji-hyuk Lim , Suk-jin Ham , Jun-sik Hwang , Chang-youl Moon
IPC分类号： H01L23/12
CPC分类号： B81C1/00301 , B81B2207/095 , H01L21/4817 , H01L21/50 , H01L2924/16235
摘要： A wafer level packaging cap for covering a device wafer with a device thereon and a fabrication method thereof are provided. The method includes operations of forming a plurality of connection grooves on a wafer, forming a seed layer on the connection grooves, forming connection parts by filling the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the top surface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to the connection parts.
摘要翻译：提供了一种用于在其上覆盖器件晶片的晶片级封装盖及其制造方法。该方法包括在晶片上形成多个连接槽的操作，在连接槽上形成种子层，通过用金属材料填充连接槽来形成连接部分，在晶片的顶表面上形成电极盖连接到连接部分，将支撑膜与其上形成有盖垫的晶片的顶表面接合，在晶片的底表面上形成空腔，以通过空腔露出连接部分，并在其上形成金属线晶片的底表面电连接到连接部分。

10. 发明授权

US07408257B2 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US07408257B2
公开(公告)日：2008-08-05
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/04
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

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