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1. 发明申请

US20070096227A1 Wafer level package for surface acoustic wave device and fabrication method thereof 有权
标题翻译：用于表面声波器件的晶片级封装及其制造方法
公开(公告)号：US20070096227A1
公开(公告)日：2007-05-03
申请号：US11415099
申请日：2006-05-02
申请人： Ji-hyuk Lim , Jun-sik Hwang , Woon-bae Kim , Suk-jin Ham , Jong-oh Kwon , Moon-chul Lee , Chang-youl Moon
发明人： Ji-hyuk Lim , Jun-sik Hwang , Woon-bae Kim , Suk-jin Ham , Jong-oh Kwon , Moon-chul Lee , Chang-youl Moon
IPC分类号： H01L29/84
CPC分类号： H03H9/1092
摘要： A wafer level package for a surface acoustic wave device and a fabrication method thereof include a SAW device formed with a SAW element on an upper surface of a device wafer; a cap wafer joined on an upper part of the SAW element; a cavity part housing the SAW element between the cap wafer and the SAW device; a cap pad formed on an upper surface of the cap wafer; and a metal line formed to penetrate through the cap wafer to electrically connect the cap pad and the SAW element, the device wafer and the cap wafer being made of the same materials.
摘要翻译：用于声表面波器件的晶片级封装及其制造方法包括在器件晶片的上表面上形成有SAW元件的SAW器件; 接合在所述SAW元件的上部的盖晶片; 在所述盖晶片和所述SAW器件之间容纳所述SAW元件的空腔部; 帽盖，形成在盖晶片的上表面上; 以及金属线，其形成为穿透盖晶片以电连接帽垫和SAW元件，器件晶片和盖晶片由相同的材料制成。

2. 发明申请

US20070085195A1 Wafer level packaging cap and fabrication method thereof 有权
标题翻译：晶圆级封装盖及其制造方法
公开(公告)号：US20070085195A1
公开(公告)日：2007-04-19
申请号：US11365838
申请日：2006-03-02
申请人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Ji-hyuk Lim , Suk-jin Ham , Jun-sik Hwang , Chang-youl Moon
发明人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Ji-hyuk Lim , Suk-jin Ham , Jun-sik Hwang , Chang-youl Moon
IPC分类号： H01L23/12
CPC分类号： B81C1/00301 , B81B2207/095 , H01L21/4817 , H01L21/50 , H01L2924/16235
摘要： A wafer level packaging cap for covering a device wafer with a device thereon and a fabrication method thereof are provided. The method includes operations of forming a plurality of connection grooves on a wafer, forming a seed layer on the connection grooves, forming connection parts by filling the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the top surface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to the connection parts.
摘要翻译：提供了一种用于在其上覆盖器件晶片的晶片级封装盖及其制造方法。该方法包括在晶片上形成多个连接槽的操作，在连接槽上形成种子层，通过用金属材料填充连接槽来形成连接部分，在晶片的顶表面上形成电极盖连接到连接部分，将支撑膜与其上形成有盖垫的晶片的顶表面接合，在晶片的底表面上形成空腔，以通过空腔露出连接部分，并在其上形成金属线晶片的底表面电连接到连接部分。

3. 发明授权

US07449366B2 Wafer level packaging cap and fabrication method thereof 有权
标题翻译：晶圆级封装盖及其制造方法
公开(公告)号：US07449366B2
公开(公告)日：2008-11-11
申请号：US11365838
申请日：2006-03-02
申请人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Ji-hyuk Lim , Suk-jin Ham , Jun-sik Hwang , Chang-youl Moon
发明人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Ji-hyuk Lim , Suk-jin Ham , Jun-sik Hwang , Chang-youl Moon
IPC分类号： H01L21/00
CPC分类号： B81C1/00301 , B81B2207/095 , H01L21/4817 , H01L21/50 , H01L2924/16235
摘要： A wafer level packaging cap for covering a device wafer with a device thereon and a fabrication method thereof are provided. The method includes operations of forming a plurality of connection grooves on a wafer, forming a seed layer on the connection grooves, forming connection parts by filling the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the top surface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to the connection parts.
摘要翻译：提供了一种用于在其上覆盖器件晶片的晶片级封装盖及其制造方法。该方法包括在晶片上形成多个连接槽的操作，在连接槽上形成种子层，通过用金属材料填充连接槽来形成连接部分，在晶片的顶表面上形成电极盖连接到连接部分，将支撑膜与其上形成有盖垫的晶片的顶表面接合，在晶片的底表面上形成空腔，以通过空腔露出连接部分，并在其上形成金属线晶片的底表面电连接到连接部分。

4. 发明授权

US07755151B2 Wafer level package for surface acoustic wave device and fabrication method thereof 有权
标题翻译：用于表面声波器件的晶片级封装及其制造方法
公开(公告)号：US07755151B2
公开(公告)日：2010-07-13
申请号：US11415099
申请日：2006-05-02
申请人： Ji-hyuk Lim , Jun-sik Hwang , Woon-bae Kim , Suk-jin Ham , Jong-oh Kwon , Moon-chul Lee , Chang-youl Moon
发明人： Ji-hyuk Lim , Jun-sik Hwang , Woon-bae Kim , Suk-jin Ham , Jong-oh Kwon , Moon-chul Lee , Chang-youl Moon
IPC分类号： H01L29/82 , H01L23/04 , H01L21/00
CPC分类号： H03H9/1092
摘要： A wafer level package for a surface acoustic wave device and a fabrication method thereof include a SAW device formed with a SAW element on an upper surface of a device wafer; a cap wafer joined on an upper part of the SAW element; a cavity part housing the SAW element between the cap wafer and the SAW device; a cap pad formed on an upper surface of the cap wafer; and a metal line formed to penetrate through the cap wafer to electrically connect the cap pad and the SAW element, the device wafer and the cap wafer being made of the same materials.
摘要翻译：用于声表面波器件的晶片级封装及其制造方法包括在器件晶片的上表面上形成有SAW元件的SAW器件; 接合在所述SAW元件的上部的盖晶片; 在所述盖晶片和所述SAW器件之间容纳所述SAW元件的空腔部; 帽盖，形成在盖晶片的上表面上; 以及金属线，其形成为穿透盖晶片以电连接帽垫和SAW元件，器件晶片和盖晶片由相同的材料制成。

5. 发明授权

US07374972B2 Micro-package, multi-stack micro-package, and manufacturing method therefor 有权
标题翻译：微封装，多堆微型封装及其制造方法
公开(公告)号：US07374972B2
公开(公告)日：2008-05-20
申请号：US11782404
申请日：2007-07-24
申请人： Jong-oh Kwon , Woon-bae Kim , In-sang Song , Ji-hyuk Lim , Suk-jin Ham , Byung-gil Jeong
发明人： Jong-oh Kwon , Woon-bae Kim , In-sang Song , Ji-hyuk Lim , Suk-jin Ham , Byung-gil Jeong
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/053 , B81C1/00269 , H01L23/055 , H01L23/10 , H01L23/147 , H01L23/49816 , H01L23/564 , H01L24/02 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/11831 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/274 , H01L2224/2929 , H01L2224/293 , H01L2224/48463 , H01L2224/83851 , H01L2224/9202 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06586 , H01L2225/1035 , H01L2924/00011 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/30105 , H01L2224/29075 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs. As stated above, the present invention has advantages of guaranteeing the hermetical sealing since the above layers prevent moisture absorption from outside at the same time of lowering possibility of damages to the device inside the package since the processing temperature drops below 150° upon wafer bonding due to the use of the polymer substance as a bonding substance.
摘要翻译：提供微型封装，多堆叠微型封装及其制造方法。根据本发明的微型封装包括用于安装器件的器件基板，作为电路模块; 保护装置的保护帽; 通过在器件基板上的预定区域上图案化而形成的结合物质将器件基板和保护盖接合; 形成在器件基板的一部分上的层和粘合物质的保护盖的一部分和外侧; 通过蚀刻掉保护盖的另一部分并且通过接合物质电连接到器件基板的上表面而形成的通孔; 在通孔上形成的阻挡金属（UBM）; 以及形成在UBM上的作为外部信号的连接端子的焊料保险杠。如上所述，本发明具有保证气密密封的优点，因为上述层防止从外部吸湿，同时降低了对包装内部装置的损坏的可能性，因为处理温度在晶片接合后下降到150°以下涉及使用聚合物物质作为结合物质。

6. 发明申请

US20070264757A1 MICRO-PACKAGE, MULTI-STACK MICRO-PACKAGE, AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：微型封装，多层微封装及其制造方法
公开(公告)号：US20070264757A1
公开(公告)日：2007-11-15
申请号：US11782404
申请日：2007-07-24
申请人： Jong-oh KWON , Woon-Bae Kim , In-sang Song , Ji-hyuk Lim , Suk-jin Ham , Byung-gil Jeong
发明人： Jong-oh KWON , Woon-Bae Kim , In-sang Song , Ji-hyuk Lim , Suk-jin Ham , Byung-gil Jeong
IPC分类号： H01L21/00
CPC分类号： H01L23/053 , B81C1/00269 , H01L23/055 , H01L23/10 , H01L23/147 , H01L23/49816 , H01L23/564 , H01L24/02 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/11831 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/274 , H01L2224/2929 , H01L2224/293 , H01L2224/48463 , H01L2224/83851 , H01L2224/9202 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06586 , H01L2225/1035 , H01L2924/00011 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/30105 , H01L2224/29075 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs. As stated above, the present invention has advantages of guaranteeing the hermetical sealing since the above layers prevent moisture absorption from outside at the same time of lowering possibility of damages to the device inside the package since the processing temperature drops below 150° upon wafer bonding due to the use of the polymer substance as a bonding substance.
摘要翻译：提供微型封装，多堆叠微型封装及其制造方法。根据本发明的微型封装包括用于安装器件的器件基板，作为电路模块; 保护装置的保护帽; 通过在器件基板上的预定区域上图案化而形成的结合物质将器件基板和保护盖接合; 形成在器件基板的一部分上的层和粘合物质的保护盖的一部分和外侧; 通过蚀刻掉保护盖的另一部分并且通过接合物质电连接到器件基板的上表面而形成的通孔; 在通孔上形成的阻挡金属（UBM）; 以及形成在UBM上的作为外部信号的连接端子的焊料保险杠。如上所述，本发明具有保证气密密封的优点，因为上述层防止从外部吸湿，同时降低了对包装内部装置的损坏的可能性，因为处理温度在晶片接合后下降到150°以下涉及使用聚合物物质作为结合物质。

7. 发明授权

US07285865B2 Micro-package, multi-stack micro-package, and manufacturing method therefor 有权
公开(公告)号：US07285865B2
公开(公告)日：2007-10-23
申请号：US11396544
申请日：2006-04-04
申请人： Jong-oh Kwon , Woon-bae Kim , In-sang Song , Ji-hyuk Lim , Suk-jin Ham , Byung-gil Jeong
发明人： Jong-oh Kwon , Woon-bae Kim , In-sang Song , Ji-hyuk Lim , Suk-jin Ham , Byung-gil Jeong
IPC分类号： H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/053 , B81C1/00269 , H01L23/055 , H01L23/10 , H01L23/147 , H01L23/49816 , H01L23/564 , H01L24/02 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/11831 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/274 , H01L2224/2929 , H01L2224/293 , H01L2224/48463 , H01L2224/83851 , H01L2224/9202 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06586 , H01L2225/1035 , H01L2924/00011 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/30105 , H01L2224/29075 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs. As stated above, the present invention has advantages of guaranteeing the hermetical sealing since the above layers prevent moisture absorption from outside at the same time of lowering possibility of damages to the device inside the package since the processing temperature drops below 150° upon wafer bonding due to the use of the polymer substance as a bonding substance.

8. 发明申请

US20070012655A1 Micro-package, multi-stack micro-package, and manufacturing method therefor 有权
标题翻译：微封装，多堆微型封装及其制造方法
公开(公告)号：US20070012655A1
公开(公告)日：2007-01-18
申请号：US11396544
申请日：2006-04-04
申请人： Jong-oh Kwon , Woon-bae Kim , In-sang Song , Ji-hyuk Lim , Suk-jin Ham , Byung-gil Jeong
发明人： Jong-oh Kwon , Woon-bae Kim , In-sang Song , Ji-hyuk Lim , Suk-jin Ham , Byung-gil Jeong
IPC分类号： H01B13/00 , H01L21/30 , H01L21/00 , H01L23/52
CPC分类号： H01L23/053 , B81C1/00269 , H01L23/055 , H01L23/10 , H01L23/147 , H01L23/49816 , H01L23/564 , H01L24/02 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/11831 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/274 , H01L2224/2929 , H01L2224/293 , H01L2224/48463 , H01L2224/83851 , H01L2224/9202 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06586 , H01L2225/1035 , H01L2924/00011 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/30105 , H01L2224/29075 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs. As stated above, the present invention has advantages of guaranteeing the hermetical sealing since the above layers prevent moisture absorption from outside at the same time of lowering possibility of damages to the device inside the package since the processing temperature drops below 150° upon wafer bonding due to the use of the polymer substance as a bonding substance.
摘要翻译：提供微型封装，多堆叠微型封装及其制造方法。根据本发明的微型封装包括用于安装器件的器件基板，作为电路模块; 保护装置的保护帽; 通过在器件基板上的预定区域上图案化而形成的结合物质将器件基板和保护盖接合; 形成在器件基板的一部分上的层和粘合物质的保护盖的一部分和外侧; 通过蚀刻掉保护盖的另一部分并且通过接合物质电连接到器件基板的上表面而形成的通孔; 在通孔上形成的阻挡金属（UBM）; 以及形成在UBM上的作为外部信号的连接端子的焊料保险杠。如上所述，本发明具有保证气密密封的优点，因为上述层防止从外部吸湿，同时降低了对包装内部装置的损坏的可能性，因为处理温度在晶片接合后下降到150°以下涉及使用聚合物物质作为结合物质。

9. 发明申请

US20060273444A1 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US20060273444A1
公开(公告)日：2006-12-07
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/48
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

10. 发明授权

US07408257B2 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US07408257B2
公开(公告)日：2008-08-05
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/04
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

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