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1. 发明申请

US20160343660A1 WIRING STRUCTURES AND SEMICONDUCTOR DEVICES 审中-公开
标题翻译：接线结构和半导体器件
公开(公告)号：US20160343660A1
公开(公告)日：2016-11-24
申请号：US15073640
申请日：2016-03-17
申请人： Jun-Jung KIM , Young-Bae KIM , Jong-Sam KIM , Jin-Hyeung PARK , Jeong-Hoon AHN , Hyeok-Sang OH , Kyoung-Woo LEE , Hyo-Seon LEE , Suk-Hee JANG
发明人： Jun-Jung KIM , Young-Bae KIM , Jong-Sam KIM , Jin-Hyeung PARK , Jeong-Hoon AHN , Hyeok-Sang OH , Kyoung-Woo LEE , Hyo-Seon LEE , Suk-Hee JANG
IPC分类号： H01L23/535 , H01L23/528 , H01L23/522 , H01L27/088
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76873 , H01L21/76882 , H01L21/823475 , H01L23/485 , H01L23/53295 , H01L27/088
摘要： A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.
摘要翻译：布线结构包括衬底，衬底上的下绝缘层，下绝缘层中的下布线，覆盖下布线并包括金属电介质材料的第一蚀刻停止层，第一蚀刻停止层蚀刻停止层和下绝缘层，在第二蚀刻停止层上的绝缘中间层，以及延伸穿过绝缘中间层，第二蚀刻停止层和第一蚀刻停止层并电连接到下部绝缘层的导电图案接线。

2. 发明申请

US20070072319A1 INTEGRATED CIRCUIT CAPACITOR STRUCTURE 审中-公开
标题翻译：集成电路电容器结构
公开(公告)号：US20070072319A1
公开(公告)日：2007-03-29
申请号：US11559317
申请日：2006-11-13
申请人： Jeong-Hoon AHN , Kyungtae LEE , Mu-Kyung JUNG , Yong-Jun LEE
发明人： Jeong-Hoon AHN , Kyungtae LEE , Mu-Kyung JUNG , Yong-Jun LEE
IPC分类号： H01L21/66 , H01L21/331 , G01R31/26
CPC分类号： H01L28/55 , H01L21/76895 , H01L23/5223 , H01L27/0805 , H01L27/1085 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.
摘要翻译：本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

3. 发明申请

US20160343708A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160343708A1
公开(公告)日：2016-11-24
申请号：US15048986
申请日：2016-02-19
申请人： Jungil PARK , Jeong-Hoon AHN , Junjung KIM , Chul-Yong PARK
发明人： Jungil PARK , Jeong-Hoon AHN , Junjung KIM , Chul-Yong PARK
IPC分类号： H01L27/088 , H01L29/06 , H01L29/417 , H01L29/78 , H01L23/528 , H01L23/522
CPC分类号： H01L27/0886 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L23/485 , H01L23/5226 , H01L23/5286 , H01L27/0207 , H01L29/41791 , H01L29/66545
摘要： A semiconductor device may include a substrate, a plurality of first contact plugs, a first via and a power rail. The substrate may include first and second cell regions and a power rail region. The first and second cell regions may be disposed in a second direction, and the power rail region may be disposed between the first and second regions. The plurality of first contact plugs may be formed on the power rail region of the substrate, and may be spaced apart from each other by a first distance in a first direction crossing the second direction. The first via may commonly contact top surfaces of the first contact plugs. The power rail may be formed on the first via. The power rail may provide a voltage for the first and second cell regions through the first via and the first contact plugs.
摘要翻译：半导体器件可以包括衬底，多个第一接触插塞，第一通孔和电源轨。衬底可以包括第一和第二电池区域和电力轨道区域。第一和第二单元区域可以设置在第二方向上，并且电力轨道区域可以设置在第一和第二区域之间。多个第一接触插塞可以形成在基板的动力轨道区域上，并且可以在与第二方向交叉的第一方向上彼此间隔开第一距离。第一通孔可以通常接触第一接触插塞的顶表面。电源轨可以形成在第一通孔上。电源轨可以通过第一通孔和第一接触插头为第一和第二电池区域提供电压。

4. 发明申请

US20130130415A1 METHODS OF TESTING INTEGRATED CIRCUIT DEVICES USING FUSE ELEMENTS 有权
标题翻译：使用保险丝元件测试集成电路设备的方法
公开(公告)号：US20130130415A1
公开(公告)日：2013-05-23
申请号：US13300274
申请日：2011-11-18
申请人： Jeong-Hoon AHN , Hyun-Min Choi , Oluwafemi O. Ogunsola
发明人： Jeong-Hoon AHN , Hyun-Min Choi , Oluwafemi O. Ogunsola
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L22/14 , H01L22/20 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then “cut” by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical “open” (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate.
摘要翻译：制造集成电路器件的方法利用熔丝元件来支持制造过程中垂直集成的测试元件的顺序测试。这些方法包括在衬底上形成第一测试元件，第一熔丝和通过第一熔丝电连接到第一测试元件的第一测试焊盘。通过在第一测试元件和第一测试焊盘之间传递第一电流并通过第一熔丝来测试第一测试元件。然后通过增加第一熔丝的阻抗来将第一熔丝“切割”，其可以包括断开第一熔丝以产生电“开放”（无限阻抗）或大大增加第一熔丝的电阻（例如，通过使第通过电迁移保险丝）。然后在基板上形成第二测试元件和与第二测试元件和第一测试焊盘电连接的第二测试焊盘。

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