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1. 发明申请

US20110003450A1 METHOD FOR MANUFACTURING SEMICONDUTOR DEVICE WITH STRAINED CHANNEL 审中-公开
标题翻译：制造具有应变通道的半导体器件的方法
公开(公告)号：US20110003450A1
公开(公告)日：2011-01-06
申请号：US12646207
申请日：2009-12-23
申请人： Young-Ho LEE , Tae-Hang Ahn , Seung-Beom Baek , Jun-Hee Cho , Jeong-Seon Kim
发明人： Young-Ho LEE , Tae-Hang Ahn , Seung-Beom Baek , Jun-Hee Cho , Jeong-Seon Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/6653 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer.
摘要翻译：一种用于形成半导体器件的方法包括在硅衬底上形成栅极图案，在栅极图案的两个侧壁上形成栅极间隔物，在每个栅极间隔物的侧壁上形成虚拟栅极隔离物，形成具有倾斜通过凹槽蚀刻硅衬底沿着栅极图案下方的沟道区域的方向延伸的侧壁，通过选择性外延生长工艺用成为源极区域或漏极区域的外延膜填充凹部区域，虚拟栅极隔板。

2. 发明授权

US07585727B2 Method for fabricating semiconductor device having bulb-shaped recess gate 失效
标题翻译：制造具有灯泡形凹槽的半导体器件的方法
公开(公告)号：US07585727B2
公开(公告)日：2009-09-08
申请号：US11617595
申请日：2006-12-28
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/3083 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes etching a portion of a substrate to form a recess. A polymer layer fills a lower portion of the recess. Sidewall spacers are formed over the recess above the lower portion of the recess. The polymer layer is removed. The lower portion of the recess is isotropically etching to form a bulb-shaped recess.
摘要翻译：一种用于制造半导体器件的方法，包括蚀刻衬底的一部分以形成凹陷。聚合物层填充凹部的下部。侧壁间隔件形成在凹部的下部上方的凹部上。去除聚合物层。凹槽的下部进行各向同性蚀刻以形成灯泡状的凹部。

3. 发明申请

US20080087980A1 Semiconductor device and method for fabricating a semiconductor device 审中-公开
公开(公告)号：US20080087980A1
公开(公告)日：2008-04-17
申请号：US11999466
申请日：2007-12-04
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L25/00
CPC分类号： H01L21/76289 , H01L21/76283 , H01L21/764 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.

4. 发明授权

US08779493B2 Semiconductor device with increased channel length and method for fabricating the same 失效
标题翻译：具有增加的通道长度的半导体器件及其制造方法
公开(公告)号：US08779493B2
公开(公告)日：2014-07-15
申请号：US13252577
申请日：2011-10-04
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L29/1037 , H01L29/78
摘要： A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
摘要翻译：半导体器件包括形成在衬底的预定部分中的沟槽和沟槽下方的第一凹陷区域。场氧化物层埋入沟槽和第一凹陷区域中。有源区由场氧化物层限定，具有第一有源区和第二有源区。后者具有形成在有源区的下部的第二凹部，而不是前者。在第一有源区和第二有源区之间的边界区域上形成阶梯栅极图案。栅极图案具有其一侧延伸到第一有源区的表面并且另一侧延伸到第二有源区的表面的阶梯结构。还描述了其它实施例。

5. 发明授权

US08049262B2 Semiconductor device with increased channel length and method for fabricating the same 有权
标题翻译：具有增加的通道长度的半导体器件及其制造方法
公开(公告)号：US08049262B2
公开(公告)日：2011-11-01
申请号：US11891904
申请日：2007-08-13
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L29/1037 , H01L29/78
摘要： A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
摘要翻译：半导体器件包括形成在衬底的预定部分中的沟槽和沟槽下方的第一凹陷区域。场氧化物层埋入沟槽和第一凹陷区域中。有源区由场氧化物层限定，具有第一有源区和第二有源区。后者具有形成在有源区域的下部的第二凹部区域。在第一有源区域和第二有源区域之间的边界区域上形成阶梯栅极图案。栅极图案具有其一侧延伸到第一有源区的表面并且另一侧延伸到第二有源区的表面的台阶结构。还描述了其它实施例。

6. 发明授权

US07977749B2 Semiconductor device with increased channel area 失效
标题翻译：半导体器件通道面积增加
公开(公告)号：US07977749B2
公开(公告)日：2011-07-12
申请号：US12648227
申请日：2009-12-28
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L29/786 , H01L29/80
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/42392 , H01L29/66772 , H01L29/78639 , H01L29/78696
摘要： A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
摘要翻译：半导体器件包括限定至少四个表面的有源区，所述四个表面包括第一，第二，第三和第四表面，围绕有源区的四个表面形成的栅极绝缘层，以及围绕栅极绝缘体形成的栅电极层和有源区的四个表面。

7. 发明授权

US08236696B2 Transistor and method for fabricating the same 失效
标题翻译：晶体管及其制造方法
公开(公告)号：US08236696B2
公开(公告)日：2012-08-07
申请号：US11965708
申请日：2007-12-27
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L29/78 , H01L21/306
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7853
摘要： A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.
摘要翻译：提供了一种制造半导体器件以扩大沟道区域的方法。由于具有晶体管的柱状侧壁，沟道区域被扩大。晶体管包括在衬底上垂直突出的翅片有源区域，包围翅片有源区域的下部的隔离层以及与鳍片有源区域交叉并覆盖翅片有源区域的一部分的栅电极。隔离层被形成为包围翅片有源区的下部，并且隔离层下面的隔离层被部分去除以暴露翅片活性区的侧壁的一部分。随后，进行干蚀刻以形成具有柱/颈的侧壁。

8. 发明授权

US07638398B2 Semiconductor device with increased channel area and fabrication method thereof 失效
标题翻译：具有增加的通道面积的半导体器件及其制造方法
公开(公告)号：US07638398B2
公开(公告)日：2009-12-29
申请号：US11617500
申请日：2006-12-28
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L29/786 , H01L29/80
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/42392 , H01L29/66772 , H01L29/78639 , H01L29/78696
摘要： A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
摘要翻译：半导体器件包括限定至少四个表面的有源区，所述四个表面包括第一，第二，第三和第四表面，围绕有源区的四个表面形成的栅极绝缘层，以及围绕栅极绝缘体形成的栅电极层和有源区的四个表面。

9. 发明申请

US20070148980A1 Method for fabricating semiconductor device with bulb-shaped recess gate 失效
标题翻译：制造具有灯泡形凹槽的半导体器件的方法
公开(公告)号：US20070148980A1
公开(公告)日：2007-06-28
申请号：US11413189
申请日：2006-04-28
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： C23F1/00 , H01L21/311 , H01L21/302 , B44C1/22
CPC分类号： H01L29/42376 , H01L21/28114 , H01L29/66545
摘要： A method for fabricating a semiconductor device with a bulb-shaped recess gate pattern is provided. The method includes forming a plurality of oxide layers over a substrate; forming a silicon layer to cover the oxide layers; forming a mask over the silicon layer; etching the silicon layer using the mask as an etch mask to form a plurality of first recesses to expose the oxide layers; etching the oxide layers to form a plurality of second recesses; and forming a plurality of gate patterns at least partially buried into the first recesses and the second recesses.
摘要翻译：提供一种用于制造具有灯泡形凹槽栅极图案的半导体器件的方法。该方法包括在衬底上形成多个氧化物层; 形成硅层以覆盖氧化物层; 在硅层上形成掩模; 使用掩模蚀刻硅层作为蚀刻掩模以形成多个第一凹部以暴露氧化物层; 蚀刻氧化物层以形成多个第二凹槽; 以及形成至少部分地埋入所述第一凹部和所述第二凹部中的多个栅极图案。

10. 发明申请

US20120080743A1 SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL LENGTH AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：具有增加的通道长度的半导体器件及其制造方法
公开(公告)号：US20120080743A1
公开(公告)日：2012-04-05
申请号：US13252577
申请日：2011-10-04
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/1037 , H01L29/78
摘要： A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
摘要翻译：半导体器件包括形成在衬底的预定部分中的沟槽和沟槽下方的第一凹陷区域。场氧化物层埋入沟槽和第一凹陷区域中。有源区由场氧化物层限定，具有第一有源区和第二有源区。后者具有形成在有源区的下部的第二凹部，而不是前者。在第一有源区和第二有源区之间的边界区域上形成阶梯栅极图案。栅极图案具有其一侧延伸到第一有源区的表面并且另一侧延伸到第二有源区的表面的阶梯结构。还描述了其它实施例。

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