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1. 发明申请

US20120033118A1 CMOS IMAGE SENSOR HAVING WIDE DYNAMIC RANGE AND SENSING METHOD THEREOF 有权
标题翻译：具有宽动态范围的CMOS图像传感器及其感测方法
公开(公告)号：US20120033118A1
公开(公告)日：2012-02-09
申请号：US13138630
申请日：2010-03-10
申请人： Jawoong Lee , Jun hee Cho , Jong Beom Choi
发明人： Jawoong Lee , Jun hee Cho , Jong Beom Choi
IPC分类号： H04N5/374
CPC分类号： H01L27/14609 , H04N5/35554 , H04N5/37452
摘要： Disclosed are a CMOS image sensor having a wide dynamic range and a sensing method thereof. Each unit pixel of the CMOS image sensor of the present invention includes multiple processing units, so that one shuttering section for the image generation of one image frame can be divided into multiple sections to separately shutter and sample the divided sections by each processing unit. Thus, the image sensor of the present invention enables many shuttering actions to be performed in the multiple processing units, respectively, and the multiple processing units to separately sample each floating diffusion voltage caused by the shuttering actions, thereby realizing a wide dynamic range.
摘要翻译：公开了具有宽动态范围的CMOS图像传感器及其感测方法。本发明的CMOS图像传感器的每个单位像素包括多个处理单元，使得一个图像帧的图像生成的一个快门部分可以被划分为多个部分，以分别由每个处理单元快门和采样分割的部分。因此，本发明的图像传感器能够分别在多个处理单元中执行多个快门动作，并且多个处理单元分别对由快门动作引起的每个浮动扩散电压进行采样，从而实现宽的动态范围。

2. 发明申请

US20110003450A1 METHOD FOR MANUFACTURING SEMICONDUTOR DEVICE WITH STRAINED CHANNEL 审中-公开
标题翻译：制造具有应变通道的半导体器件的方法
公开(公告)号：US20110003450A1
公开(公告)日：2011-01-06
申请号：US12646207
申请日：2009-12-23
申请人： Young-Ho LEE , Tae-Hang Ahn , Seung-Beom Baek , Jun-Hee Cho , Jeong-Seon Kim
发明人： Young-Ho LEE , Tae-Hang Ahn , Seung-Beom Baek , Jun-Hee Cho , Jeong-Seon Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/6653 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer.
摘要翻译：一种用于形成半导体器件的方法包括在硅衬底上形成栅极图案，在栅极图案的两个侧壁上形成栅极间隔物，在每个栅极间隔物的侧壁上形成虚拟栅极隔离物，形成具有倾斜通过凹槽蚀刻硅衬底沿着栅极图案下方的沟道区域的方向延伸的侧壁，通过选择性外延生长工艺用成为源极区域或漏极区域的外延膜填充凹部区域，虚拟栅极隔板。

3. 发明授权

US07585727B2 Method for fabricating semiconductor device having bulb-shaped recess gate 失效
标题翻译：制造具有灯泡形凹槽的半导体器件的方法
公开(公告)号：US07585727B2
公开(公告)日：2009-09-08
申请号：US11617595
申请日：2006-12-28
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/3083 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes etching a portion of a substrate to form a recess. A polymer layer fills a lower portion of the recess. Sidewall spacers are formed over the recess above the lower portion of the recess. The polymer layer is removed. The lower portion of the recess is isotropically etching to form a bulb-shaped recess.
摘要翻译：一种用于制造半导体器件的方法，包括蚀刻衬底的一部分以形成凹陷。聚合物层填充凹部的下部。侧壁间隔件形成在凹部的下部上方的凹部上。去除聚合物层。凹槽的下部进行各向同性蚀刻以形成灯泡状的凹部。

4. 发明授权

US07449392B2 Semiconductor device capable of threshold voltage adjustment by applying an external voltage 失效
标题翻译：能够通过施加外部电压来阈值电压调节的半导体器件
公开(公告)号：US07449392B2
公开(公告)日：2008-11-11
申请号：US11877820
申请日：2007-10-24
申请人： Yil Wook Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
发明人： Yil Wook Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/7831 , H01L21/3065 , H01L21/3086 , H01L21/76232 , H01L21/763 , H01L21/764 , H01L21/765 , H01L21/823412 , H01L21/823481 , H01L27/0214 , H01L27/10873 , H01L29/0657 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.
摘要翻译：半导体器件具有硅衬底，其中在两个器件隔离膜之间形成有源区，并且在有源区的表面上形成栅极。硅衬底在靠近器件隔离膜的一侧上的有源区的表面下方的有源区中具有横向蚀刻的部分。绝缘膜形成在硅衬底的横向蚀刻部分上。在绝缘膜上形成导电电极，施加外部电压以调整阈值电压。器件隔离膜形成在导电电极上。在器件隔离膜和导电电极之间不存在或存在一些空穴腔。

5. 发明申请

US20080087980A1 Semiconductor device and method for fabricating a semiconductor device 审中-公开
公开(公告)号：US20080087980A1
公开(公告)日：2008-04-17
申请号：US11999466
申请日：2007-12-04
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L25/00
CPC分类号： H01L21/76289 , H01L21/76283 , H01L21/764 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.

6. 发明授权

US06836634B2 Developer unit of electrophotographic image forming apparatus 失效
标题翻译：电子照相成像设备的显影单元
公开(公告)号：US06836634B2
公开(公告)日：2004-12-28
申请号：US10255073
申请日：2002-09-26
申请人： Seung-young Byun , Jun-hee Cho
发明人： Seung-young Byun , Jun-hee Cho
IPC分类号： G03G1508
CPC分类号： G03G15/0812
摘要： A developer unit of an electrophotographic image forming apparatus includes a blocking blade having a magnetic fluid and a magnet. The magnetic fluid contacts a developer roller and the metering blade to prevent a developer from flowing to both ends of the metering blade. The magnetic fluid is fixed to the magnet which applies a pressure to the magnetic fluid so that the magnetic fluid contacts the developer roller and the metering blade. Since the magnetic fluid contacts the developer, wear of elements of the developer unit can be reduced, thereby securing durability of the developer unit. Also, a wrap-around phenomenon of the developer can be prevented.
摘要翻译：电子照相图像形成装置的显影单元包括具有磁性流体和磁体的阻挡刮板。磁性流体接触显影辊和计量刀片，以防止显影剂流到计量刀片的两端。磁性流体固定在磁体上，该磁体向磁性流体施加压力，使得磁性流体接触显影辊和计量刮板。由于磁性流体与显影剂接触，所以可以减少显影剂单元的元件磨损，从而确保显影剂单元的耐久性。此外，可以防止显影剂的回绕现象。

7. 发明授权

US06823161B2 Developer of electrophotographic image forming system 失效
标题翻译：电子照相成像系统的显影剂
公开(公告)号：US06823161B2
公开(公告)日：2004-11-23
申请号：US10153227
申请日：2002-05-23
申请人： Jun-hee Cho , Geun-yong Park
发明人： Jun-hee Cho , Geun-yong Park
IPC分类号： G03G1510
CPC分类号： G03G15/104 , G03G2215/0119
摘要： A developer, for an electrophotographic image forming system, includes a developer container for storing developing solution, a developing roller which is partially soaked in the developing solution stored in the developer container and installed to rotate in an opposite direction of a photosensitive medium, a cleaning roller, which is soaked in the developing solution, is installed to rotate opposite to the developing roller and removes the developing solution remaining on the surface of the developing roller, and a developing solution agitator, which agitates the developing solution, and thereby keeps the developing solution in uniform concentration. The efficiency of circulation of the developing solution can be increased by upward and downward circulating the developing solution with high concentration stored in the developer container, and the developing solution can be kept in uniform concentration by preventing the developing solution with high concentration from being deposited at the bottom of the developer container.
摘要翻译：用于电子照相图像形成系统的显影剂包括用于存储显影液的显影剂容器，显影辊，其部分地浸泡在存储在显影剂容器中的显影液中，并安装成沿与感光介质相反的方向旋转，清洁浸渍在显影液中的滚筒被安装成与显影辊相反地旋转，并且除去残留在显影辊表面上的显影液和搅拌显影液的显影液搅拌器，从而保持显影溶液均匀浓缩。可以通过向存储在显影剂容器中的高浓度的向上和向下循环显影溶液的循环效率来提高显影液的循环效率，并且可以通过防止高浓度的显影溶液沉积在显影剂容器中而使显影液保持均匀的浓度开发者容器的底部。

8. 发明授权

US08779493B2 Semiconductor device with increased channel length and method for fabricating the same 失效
标题翻译：具有增加的通道长度的半导体器件及其制造方法
公开(公告)号：US08779493B2
公开(公告)日：2014-07-15
申请号：US13252577
申请日：2011-10-04
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L29/1037 , H01L29/78
摘要： A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having first active region and a second active region. The latter has a second recess region formed in lower portion of the active region than the former. A step gate pattern is formed on border region between the first active region and the second active region. The gate pattern has step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
摘要翻译：半导体器件包括形成在衬底的预定部分中的沟槽和沟槽下方的第一凹陷区域。场氧化物层埋入沟槽和第一凹陷区域中。有源区由场氧化物层限定，具有第一有源区和第二有源区。后者具有形成在有源区的下部的第二凹部，而不是前者。在第一有源区和第二有源区之间的边界区域上形成阶梯栅极图案。栅极图案具有其一侧延伸到第一有源区的表面并且另一侧延伸到第二有源区的表面的阶梯结构。还描述了其它实施例。

9. 发明授权

US08049262B2 Semiconductor device with increased channel length and method for fabricating the same 有权
标题翻译：具有增加的通道长度的半导体器件及其制造方法
公开(公告)号：US08049262B2
公开(公告)日：2011-11-01
申请号：US11891904
申请日：2007-08-13
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L29/1037 , H01L29/78
摘要： A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first active region and a second active region. The latter has a second recess region formed in a lower portion of the active region than the former. A step gate pattern is formed on a border region between the first active region and the second active region. The gate pattern has a step structure whose one side extends to a surface of the first active region and the other side extends to a surface of the second active region. Other embodiments are also described.
摘要翻译：半导体器件包括形成在衬底的预定部分中的沟槽和沟槽下方的第一凹陷区域。场氧化物层埋入沟槽和第一凹陷区域中。有源区由场氧化物层限定，具有第一有源区和第二有源区。后者具有形成在有源区域的下部的第二凹部区域。在第一有源区域和第二有源区域之间的边界区域上形成阶梯栅极图案。栅极图案具有其一侧延伸到第一有源区的表面并且另一侧延伸到第二有源区的表面的台阶结构。还描述了其它实施例。

10. 发明授权

US07977749B2 Semiconductor device with increased channel area 失效
标题翻译：半导体器件通道面积增加
公开(公告)号：US07977749B2
公开(公告)日：2011-07-12
申请号：US12648227
申请日：2009-12-28
申请人： Jun-Hee Cho
发明人： Jun-Hee Cho
IPC分类号： H01L29/786 , H01L29/80
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/42392 , H01L29/66772 , H01L29/78639 , H01L29/78696
摘要： A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
摘要翻译：半导体器件包括限定至少四个表面的有源区，所述四个表面包括第一，第二，第三和第四表面，围绕有源区的四个表面形成的栅极绝缘层，以及围绕栅极绝缘体形成的栅电极层和有源区的四个表面。

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