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1. 发明申请

US20060273431A1 Interconnects having sealing structures to enable selective metal capping layers 有权
公开(公告)号：US20060273431A1
公开(公告)日：2006-12-07
申请号：US11144576
申请日：2005-06-03
申请人： Jun He , Kevin Fischer , Ying Zhou , Peter Moon
发明人： Jun He , Kevin Fischer , Ying Zhou , Peter Moon
IPC分类号： H01L23/52 , H01L21/469
CPC分类号： H01L21/76849 , H01L21/0217 , H01L21/02252 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76844 , H01L21/76856 , H01L21/76865 , H01L21/76877 , H01L21/76888 , H01L23/5283 , H01L23/53209 , H01L23/53228 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

2. 发明授权

US06908829B2 Method of forming an air gap intermetal layer dielectric (ILD) by utilizing a dielectric material to bridge underlying metal lines 有权
标题翻译：通过利用介电材料桥接下面的金属线形成气隙金属间电介质（ILD）的方法
公开(公告)号：US06908829B2
公开(公告)日：2005-06-21
申请号：US10094875
申请日：2002-03-11
申请人： Makarem A. Hussein , Peter Moon , Jim Powers , Kevin P. O'Brien
发明人： Makarem A. Hussein , Peter Moon , Jim Powers , Kevin P. O'Brien
IPC分类号： H01L23/522 , H01L21/76 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an air gap intermetal layer dielectric (ILD) to reduce capacitive coupling between electrical conductors in proximity. The method entails forming first and second electrical conductors over a substrate, wherein the electrical conductors are laterally spaced apart by a gap. Then, forming a gap bridging dielectric layer that extends over the first electrical conductor, the gap, and the second electrical conductor. In order to form a bridge from one electrical conductor to the other electrical conductor, the gap bridging dielectric materials should have poor gap filling characteristics. This can be attained by selecting and/or modifying a dielectric material to have a sufficiently high molecular weight and/or surface tension characteristic such that the material does not substantially sink into the gap. An example of such a material is a spin-on-polymer with a surfactant and/or other additives.
摘要翻译：一种形成气隙金属间电介质（ILD）的方法，以减少接近的电导体之间的电容耦合。该方法需要在衬底上形成第一和第二电导体，其中电导体横向间隔开间隙。然后，形成在第一电导体，间隙和第二电导体上延伸的间隙桥接电介质层。为了形成从一个电导体到另一个电导体的桥接，桥接介电材料的间隙应具有差的间隙填充特性。这可以通过选择和/或改性电介质材料来实现，以具有足够高的分子量和/或表面张力特性，使得材料基本上不会沉入间隙。这种材料的一个实例是具有表面活性剂和/或其它添加剂的旋涂聚合物。

3. 发明授权

US06707120B1 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US06707120B1
公开(公告)日：2004-03-16
申请号：US09097991
申请日：1998-06-16
申请人： Payman Aminzadeh , Reza Arghavani , Peter Moon
发明人： Payman Aminzadeh , Reza Arghavani , Peter Moon
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/3144 , H01L29/4983 , H01L29/6656
摘要： A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.
摘要翻译：公开了一种制造具有增加的抗热载体损伤的场效应晶体管的方法。在栅电极上生长氧化物。该氧化物通过氮化和退火得到加强。在轻掺杂漏极注入之后，沉积第二侧面氧化物和共形氮化物层。然后，各向异性蚀刻共形氮化物以形成用于掩蔽高剂量漏极植入物的间隔物。已经发现用该方法制造的NMOS过渡器比传统的轻掺杂漏极工艺对热载体损伤的敏感性低40％。此外，该方法已证明比侧氧化物被氮化并再次氧化的方法更可制造。

4. 外观设计

USD433249S Armoire 失效
公开(公告)号：USD433249S
公开(公告)日：2000-11-07
申请号：US102280
申请日：1999-03-22
申请人： Arthur Wilson , Peter Moon
设计人： Arthur Wilson , Peter Moon

5. 发明授权

US5827769A Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode 失效
标题翻译：通过对栅电极的侧壁氧化物进行氮化和退火来制造具有增加的热载流子电阻的晶体管的方法
公开(公告)号：US5827769A
公开(公告)日：1998-10-27
申请号：US754219
申请日：1996-11-20
申请人： Payman Aminzadeh , Reza Arghavani , Peter Moon
发明人： Payman Aminzadeh , Reza Arghavani , Peter Moon
IPC分类号： H01L21/314 , H01L21/336 , H01L29/49 , H01L21/31
CPC分类号： H01L29/6659 , H01L21/3144 , H01L29/4983 , H01L29/6656
摘要： A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.
摘要翻译：公开了一种制造具有增加的抗热载体损伤的场效应晶体管的方法。在栅电极上生长氧化物。该氧化物通过氮化和退火得到加强。在轻掺杂漏极注入之后，沉积第二侧面氧化物和共形氮化物层。然后，各向异性蚀刻共形氮化物以形成用于掩蔽高剂量漏极植入物的间隔物。已经发现用该方法制造的NMOS过渡器比传统的轻掺杂漏极工艺对热载体损伤的敏感性低40％。此外，该方法已证明比侧氧化物被氮化并再次氧化的方法更可制造。

6. 发明申请

US20070284744A1 Apparatus for an improved air gap interconnect structure 有权
标题翻译：用于改进气隙互连结构的装置
公开(公告)号：US20070284744A1
公开(公告)日：2007-12-13
申请号：US11893869
申请日：2007-08-15
申请人： Valery Dubin , Peter Moon
发明人： Valery Dubin , Peter Moon
IPC分类号： H01L23/528
CPC分类号： H01L21/76843 , H01L21/7682 , H01L21/76849 , H01L21/7685 , H01L21/76879 , H01L23/5222 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.
摘要翻译：在一个实施例中，一种装置包括具有在层间电介质（ILD）中形成的至少一个互连的第一层，在第一层上形成的具有第二至少一个互连的第二层，在第二层上形成的第三层，第三层限定第二至少一个互连和第三层之间的至少一个空气间隙，以及至少一个分流器，其选择性地覆盖第一和第二至少一个互连。在另一个实施例中，一种方法包括形成包括ILD和第一至少一个互连的第一层，在第一层上形成第二层，第二层具有第二至少一个互连，在第一层上沉积至少一个分流以及第二至少一个互连，在所述第二层上形成第三层，以及蒸发所述第二层的一部分以在所述第二至少一个互连和所述第三层之间产生至少一个空气间隙。

7. 发明授权

US07279423B2 Forming a copper diffusion barrier 有权
标题翻译：形成铜扩散屏障
公开(公告)号：US07279423B2
公开(公告)日：2007-10-09
申请号：US10284576
申请日：2002-10-31
申请人： Steven W. Johnston , Valery M. Dubin , Michael L. McSwiney , Peter Moon
发明人： Steven W. Johnston , Valery M. Dubin , Michael L. McSwiney , Peter Moon
IPC分类号： H01L21/00
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/288 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
摘要翻译：贵金属可用作非氧化扩散阻挡层，以防止铜线扩散。扩散阻挡层可以由在可氧化扩散阻挡层上形成在粘附促进层上或由贵金属盖形成的贵金属形成。铜线也可以用贵金属覆盖。

8. 发明申请

US20060076678A1 Thick metal layer integrated process flow to improve power delivery and mechanical buffering 审中-公开
标题翻译：厚金属层集成工艺流程，以改善动力传递和机械缓冲
公开(公告)号：US20060076678A1
公开(公告)日：2006-04-13
申请号：US11281709
申请日：2005-11-16
申请人： Sarah Kim , Bob Martell , David Ayers , R. List , Peter Moon , Steven Towle , Anna George
发明人： Sarah Kim , Bob Martell , David Ayers , R. List , Peter Moon , Steven Towle , Anna George
IPC分类号： H01L23/48
CPC分类号： H01L24/12 , H01L21/76838 , H01L23/36 , H01L23/49816 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L24/11 , H01L24/16 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/05666 , H01L2224/13099 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014
摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
摘要翻译：在芯片或晶片级的受控崩溃芯片连接（C 4）凸起处制造具有一个或多个厚金属层的互连结构的工艺流程。互连结构可以用在微处理器的后端互连中。一个或多个集成的厚金属层可以改善功率传递并且降低在管芯/封装接口处的管芯的机械应力。

9. 发明申请

US20050181593A1 SELECTIVELY CONVERTED INTER-LAYER DIELECTRIC 失效
标题翻译：选择性转换层间电介质
公开(公告)号：US20050181593A1
公开(公告)日：2005-08-18
申请号：US10302073
申请日：2002-11-21
申请人： Jihperng Leu , Grant Kloster , David Gracias , Lee Rockford , Peter Moon , Chris Barns
发明人： Jihperng Leu , Grant Kloster , David Gracias , Lee Rockford , Peter Moon , Chris Barns
IPC分类号： H01L21/312 , H01L21/316 , H01L21/768 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76835 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/312 , H01L21/3124 , H01L21/31695 , H01L21/76807 , H01L21/7682
摘要： An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.
摘要翻译：公开了一种层间电介质结构及其制造方法。形成初始包含多孔基质和致孔剂的复合介电层。在其它处理处理之后，致孔剂从多孔基体的至少一部分分解和除去，留下由多孔基质定义的空隙，其中先前由致孔剂占据的区域。所得结构由于孔隙率和包含多孔基质和致孔剂的材料而具有期望的低k值。复合介电层可以与具有不同孔隙率，尺寸和材料性质的其它电介质层一起使用，以提供不同的机械和电气性能轮廓。

10. 发明授权

US08227335B2 Forming a copper diffusion barrier 有权
标题翻译：形成铜扩散屏障
公开(公告)号：US08227335B2
公开(公告)日：2012-07-24
申请号：US11897862
申请日：2007-08-31
申请人： Steven W. Johnston , Valery M. Dubin , Michael L. McSwiney , Peter Moon
发明人： Steven W. Johnston , Valery M. Dubin , Michael L. McSwiney , Peter Moon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/288 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
摘要翻译：贵金属可用作非氧化扩散阻挡层，以防止铜线扩散。扩散阻挡层可以由在可氧化扩散阻挡层上形成在粘附促进层上或由贵金属盖形成的贵金属形成。铜线也可以用贵金属覆盖。

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