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    • 3. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    • 半导体集成电路设备
    • US20100259316A1
    • 2010-10-14
    • US12623794
    • 2009-11-23
    • Tetsuya FujitaYousuke Hagiwara
    • Tetsuya FujitaYousuke Hagiwara
    • G05F1/10
    • H03K19/0016H03K19/00361
    • A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.
    • 一种半导体集成电路器件,包括:至少一个第一晶体管,被配置为控制输入电源线与输出电源线之间的电导;至少一个第二晶体管,被配置为控制输入电力线与输出电力线之间的电导;第一缓冲器配置 提供用于驱动所述至少一个第一晶体管的第一控制信号到连接到所述至少一个第一晶体管的第一控制线;第二缓冲器,被配置为产生用于在接收到所述至少一个第一晶体管时驱动所述至少一个第二晶体管的第二控制信号 第一控制信号通过第一控制线提供并将第二控制信号提供给连接到至少一个第二晶体管的第二控制线,以及连接在第一控制线和输出电源线之间的至少一个电容器。
    • 4. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US07969237B2
    • 2011-06-28
    • US12623794
    • 2009-11-23
    • Tetsuya FujitaYousuke Hagiwara
    • Tetsuya FujitaYousuke Hagiwara
    • G05F1/10
    • H03K19/0016H03K19/00361
    • A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.
    • 一种半导体集成电路器件,包括:至少一个第一晶体管,被配置为控制输入电源线与输出电源线之间的电导;至少一个第二晶体管,被配置为控制输入电力线与输出电力线之间的电导;第一缓冲器配置 提供用于驱动所述至少一个第一晶体管的第一控制信号到连接到所述至少一个第一晶体管的第一控制线;第二缓冲器,被配置为产生用于在接收到所述至少一个第一晶体管时驱动所述至少一个第二晶体管的第二控制信号 第一控制信号通过第一控制线提供并将第二控制信号提供给连接到至少一个第二晶体管的第二控制线,以及连接在第一控制线和输出电源线之间的至少一个电容器。