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1. 发明申请

US20050179141A1 Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer 有权
公开(公告)号：US20050179141A1
公开(公告)日：2005-08-18
申请号：US11095006
申请日：2005-03-31
申请人： Ju-young Yun , Gil-heyun Choi , Byung-hee Kim , Jong-myeong Lee , Seung-gil Yang , Jung-hun Seo
发明人： Ju-young Yun , Gil-heyun Choi , Byung-hee Kim , Jong-myeong Lee , Seung-gil Yang , Jung-hun Seo
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L21/4763 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76846 , H01L21/76856 , H01L21/76876 , H01L21/76879 , H01L21/76882 , H01L2221/1089
摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

2. 发明授权

US07384866B2 Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer 有权
标题翻译：通过处理阻挡金属层形成半导体器件的金属互连的方法
公开(公告)号：US07384866B2
公开(公告)日：2008-06-10
申请号：US11095006
申请日：2005-03-31
申请人： Ju-young Yun , Gil-heyun Choi , Byung-hee Kim , Jong-myeong Lee , Seung-gil Yang , Jung-hun Seo
发明人： Ju-young Yun , Gil-heyun Choi , Byung-hee Kim , Jong-myeong Lee , Seung-gil Yang , Jung-hun Seo
IPC分类号： H01L21/4763 , H01L21/44 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76846 , H01L21/76856 , H01L21/76876 , H01L21/76879 , H01L21/76882 , H01L2221/1089
摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.
摘要翻译：半导体器件的金属互连通过在衬底上形成包括孔的电介质图案，并在孔的外部和电介质层图案上形成阻挡金属层来制造。至少一些阻挡金属层被氧化。在孔的氧化阻挡金属层上选择性地形成抗成核层，该氧化的阻挡金属层露出孔中的氧化的阻挡金属层。然后在孔中的暴露的氧化阻挡层上选择性地形成金属层。

3. 发明授权

US06955983B2 Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer 有权
标题翻译：通过处理阻挡金属层形成半导体器件的金属互连的方法
公开(公告)号：US06955983B2
公开(公告)日：2005-10-18
申请号：US10373368
申请日：2003-02-24
申请人： Ju-young Yun , Gil-heyun Choi , Byung-hee Kim , Jong-myeong Lee , Seung-gil Yang , Jung-hun Seo
发明人： Ju-young Yun , Gil-heyun Choi , Byung-hee Kim , Jong-myeong Lee , Seung-gil Yang , Jung-hun Seo
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76846 , H01L21/76856 , H01L21/76876 , H01L21/76879 , H01L21/76882 , H01L2221/1089
摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.
摘要翻译：半导体器件的金属互连通过在衬底上形成包括孔的电介质图案，并在孔的外部和电介质层图案上形成阻挡金属层来制造。至少一些阻挡金属层被氧化。在孔的氧化阻挡金属层上选择性地形成抗成核层，该氧化的阻挡金属层露出孔中的氧化的阻挡金属层。然后在孔中的暴露的氧化阻挡层上选择性地形成金属层。

4. 发明授权

US06951814B2 Methods for forming a metal wiring layer on an integrated circuit device at reduced temperatures 有权
标题翻译：在降低的温度下在集成电路器件上形成金属布线层的方法
公开(公告)号：US06951814B2
公开(公告)日：2005-10-04
申请号：US10649154
申请日：2003-08-27
申请人： Byung-hee Kim , Gil-heyun Choi , Ju-young Yun , Jung-hun Seo
发明人： Byung-hee Kim , Gil-heyun Choi , Ju-young Yun , Jung-hun Seo
IPC分类号： H01L21/28 , B05D5/12 , C23C16/00 , H01L21/285 , H01L21/3205 , H01L21/44 , H01L21/768
CPC分类号： H01L21/28556 , H01L21/2855 , H01L21/32051 , H01L21/7684 , H01L21/76877
摘要： Methods of forming a metal wiring layer on an integrated circuit include forming an insulating pattern including a recess region on an integrated circuit substrate. A metal layer is formed in the recess region and on a top surface of the insulting pattern. The metal layer is removed from the top surface of the insulating pattern adjacent the recess region and from an upper portion of the recess region. An aluminum film is formed on the metal layer at a process temperature less than a reflow temperature of the metal layer to substantially fill the upper portion of the recess region after removing the metal layer. A metal film is formed on the aluminum film at a process temperature less than the reflow temperature of the etched metal layer.
摘要翻译：在集成电路上形成金属布线层的方法包括在集成电路基板上形成包括凹部区域的绝缘图案。在凹陷区域和绝缘图案的顶表面上形成金属层。金属层从绝缘图案的顶表面与凹陷区域相邻并且从凹陷区域的上部移除。在金属层上以低于金属层的回流温度的工艺温度形成铝膜，以在去除金属层之后基本上填充凹部区域的上部。在低于蚀刻金属层的回流温度的工艺温度下，在铝膜上形成金属膜。

5. 发明授权

US06849555B2 Wafer processing apparatus and wafer processing method using the same 有权
标题翻译：晶圆加工装置及使用其的晶片加工方法
公开(公告)号：US06849555B2
公开(公告)日：2005-02-01
申请号：US10449522
申请日：2003-05-30
申请人： Jong-myeong Lee , Byung-hee Kim , Myoung bum Lee , Ju-young Yun , Gil-heyun Choi
发明人： Jong-myeong Lee , Byung-hee Kim , Myoung bum Lee , Ju-young Yun , Gil-heyun Choi
IPC分类号： C23C14/56 , C23C16/44 , H01L21/00 , H01L21/02 , H01L21/285 , H01L21/302 , H01L21/461 , H01L21/677 , H01L21/768
CPC分类号： H01L21/67167 , H01L21/2855 , H01L21/28556 , H01L21/67017 , H01L21/67201 , H01L21/67739 , H01L21/76882 , H01L21/76888 , Y10S438/974
摘要： An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.
摘要翻译：提供了可用于形成具有多层结构的金属布线层和使用其的晶片处理方法的集成的原位簇型晶片处理装置。晶片处理装置包括可以排出并具有多个闸阀的传送室，多个真空处理室，每个真空处理室可以经由一个闸阀连接到传送室;以及负载锁定室，其可以被排出并且可连接到用于将氧基气体进料到负载锁定室中的第一气体供给管线。在晶片处理方法中，在一个真空处理室中的晶片上形成预定层。晶片上的预定层在负载锁定室或氧气氛室中被氧化。

6. 发明授权

US06586340B2 Wafer processing apparatus and wafer processing method using the same 有权
公开(公告)号：US06586340B2
公开(公告)日：2003-07-01
申请号：US10098029
申请日：2002-03-13
申请人： Jong-myeong Lee , Byung-hee Kim , Myoung bum Lee , Ju-young Yun , Gil-heyun Choi
发明人： Jong-myeong Lee , Byung-hee Kim , Myoung bum Lee , Ju-young Yun , Gil-heyun Choi
IPC分类号： H01L21302
CPC分类号： H01L21/67167 , H01L21/2855 , H01L21/28556 , H01L21/67017 , H01L21/67201 , H01L21/67739 , H01L21/76882 , H01L21/76888 , Y10S438/974
摘要： An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

7. 发明授权

US06391769B1 Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby 有权
标题翻译：用于在半导体器件中形成金属互连的方法和由此制造的互连结构
公开(公告)号：US06391769B1
公开(公告)日：2002-05-21
申请号：US09525154
申请日：2000-03-14
申请人： Jong-myeong Lee , Hyun-seok Lim , Byung-hee Kim , Gil-heyun Choi , Sang-in Lee
发明人： Jong-myeong Lee , Hyun-seok Lim , Byung-hee Kim , Gil-heyun Choi , Sang-in Lee
IPC分类号： H01L214763
CPC分类号： H01L21/76855 , H01L21/28562 , H01L21/32051 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76879 , H01L21/76882 , H01L21/76888 , H01L2221/1089
摘要： A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio. A metal liner may be formed instead of the metal plug, followed by forming a metal layer filling the region surrounded by the metal liner, thereby forming a metal interconnection for completely filling the contact hole or groove having a high aspect ratio.
摘要翻译：一种用于形成填充高纵横比的接触孔或槽的金属互连的方法，以及由此制造的接触结构。在半导体衬底上形成具有用作接触孔的凹陷区域，通孔或沟槽的电介质层图案。在形成介电层图案的所得结构的整个表面上形成阻挡金属层。仅在阻挡金属层的非凹陷区域选择性地形成抗成核层。通过在除了凹陷区域之外的区域中形成覆盖阻挡金属层的金属层，然后在真空中自发氧化金属层，形成抗成核层。此外，抗成核层可以通过原位形成阻挡金属层和金属层，然后通过退火处理来氧化金属层而形成。随后，在由阻挡金属层包围的凹陷区域中选择性地形成金属插塞，从而形成用于完全填充接触孔或具有高纵横比的沟槽的金属互连。可以形成金属衬垫而不是金属插塞，随后形成填充由金属衬垫包围的区域的金属层，从而形成用于完全填充具有高纵横比的接触孔或槽的金属互连。

8. 发明授权

US06432820B1 Method of selectively depositing a metal layer in an opening in a dielectric layer by forming a metal-deposition-prevention layer around the opening of the dielectric layer 有权
标题翻译：通过在电介质层的开口周围形成金属沉积防止层来选择性地在电介质层的开口中沉积金属层的方法
公开(公告)号：US06432820B1
公开(公告)日：2002-08-13
申请号：US09921165
申请日：2001-08-02
申请人： Myoung-bum Lee , Jong-myeong Lee , Byung-hee Kim , Gil-heyun Choi
发明人： Myoung-bum Lee , Jong-myeong Lee , Byung-hee Kim , Gil-heyun Choi
IPC分类号： H01L2144
CPC分类号： H01L21/76856 , H01L21/28562 , H01L21/32051 , H01L21/76843 , H01L21/76876 , H01L21/76879 , H01L21/76882 , H01L21/76888 , H01L2221/1089
摘要： A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.
摘要翻译：提供了一种用于形成半导体器件的金属布线层的方法，该方法是在压力保持在大气压以下的气密空间中进行，以形成金属沉积防止层。在半导体衬底上形成层间绝缘层图案，以限定一个孔区。在真空状态下在层间电介质层图案的顶表面上形成金属膜，以露出孔区域的侧壁。金属层在气氛中被氧化，其压力在氧气氛中保持低于大气压，从而形成金属沉积防止层。在孔区域的侧壁上选择性地形成金属衬垫。在由金属衬垫和金属沉积防止层限定的孔区域内形成金属层。金属衬垫被热处理和回流。

9. 发明授权

US06602782B2 Methods for forming metal wiring layers and metal interconnects and metal interconnects formed thereby 有权
标题翻译：用于形成金属布线层和金属互连的方法以及由此形成的金属互连
公开(公告)号：US06602782B2
公开(公告)日：2003-08-05
申请号：US09862937
申请日：2001-05-22
申请人： Myoung-bum Lee , Jong-Myeong Lee , Byung-hee Kim , Gil-heyun Choi
发明人： Myoung-bum Lee , Jong-Myeong Lee , Byung-hee Kim , Gil-heyun Choi
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76834 , H01L21/76844 , H01L21/76864 , H01L21/76876 , H01L21/76882 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole. A metal liner is then formed on a portion of the electrically conductive seed layer that defines a sidewall of the constricted contact hole. Next, a metal interconnect layer is reflowed into the constricted contact hole to thereby fill and bury the contact hole.
摘要翻译：形成金属互连的方法包括在基板上形成其中具有接触孔的电绝缘层。还进行步骤以形成导电种子层。种子层在接触孔的侧壁上延伸，并且在邻近接触孔延伸的电绝缘层的上表面的一部分上延伸。种子层沿着侧壁的上部足够厚，并且沿着侧壁的下部足够薄，接触孔的上部被种子层部分地收缩，从而限定了收缩的接触孔。在种子层的在收缩的接触孔外延伸的部分上沉积抗成核层。收缩的接触孔用作掩模以抑制邻接于缩小的接触孔的底部的防着色层的沉积。然后在导电种子层的限定收缩的接触孔的侧壁的部分上形成金属衬垫。接下来，将金属互连层回流到收缩的接触孔中，从而填充并埋入接触孔。

10. 发明授权

US07897500B2 Methods for forming silicide conductors using substrate masking 有权
标题翻译：使用基板掩模形成硅化物导体的方法
公开(公告)号：US07897500B2
公开(公告)日：2011-03-01
申请号：US12276562
申请日：2008-11-24
申请人： Eun-ji Jung , Dae-yong Kim , Gil-heyun Choi , Byung-hee Kim , Woong-hee Sohn , Hyun-su Kim , Jang-hee Lee , Eun-ok Lee , Jeong-gil Lee
发明人： Eun-ji Jung , Dae-yong Kim , Gil-heyun Choi , Byung-hee Kim , Woong-hee Sohn , Hyun-su Kim , Jang-hee Lee , Eun-ok Lee , Jeong-gil Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/28052 , H01L29/66545
摘要： A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.
摘要翻译：多个间隔开的导体结构形成在半导体衬底上，每个导体结构包括导电层。绝缘垫片形成在导体结构的侧壁上。形成填充相邻绝缘间隔件之间的间隙的层间绝缘膜。去除层间绝缘层的一部分以暴露导电层的上表面。相应的外延层在导电层的相应暴露的上表面上生长，并且各自的外延层形成各自的金属硅化物层。

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