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1. 发明申请

US20090221140A1 Method of fabricating non-volatile memory device having separate charge trap patterns 失效
标题翻译：制造具有单独的电荷陷阱图案的非易失性存储器件的方法
公开(公告)号：US20090221140A1
公开(公告)日：2009-09-03
申请号：US12453419
申请日：2009-05-11
申请人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
发明人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
IPC分类号： H01L21/28
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/78 , H01L29/7851 , H01L29/792
摘要： A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.
摘要翻译：非易失性存储器件防止电荷扩展。非易失性存储器件包括半导体衬底中的隔离沟槽，隔离层部分地填充由隔离沟槽限定的第一和第二鳍片之间的隔离沟槽，跨越第一鳍片和第二鳍片的控制栅极电极，第一电荷陷阱图案在第一鳍片和控制栅电极之间，以及第二鳍片和控制栅电极之间的第二电荷陷阱图案。

2. 发明申请

US20080105919A1 Non-volatile memory device having separate charge trap patterns and method of fabricating the same 审中-公开
标题翻译：具有分离的电荷陷阱图案的非易失性存储器件及其制造方法
公开(公告)号：US20080105919A1
公开(公告)日：2008-05-08
申请号：US11819850
申请日：2007-06-29
申请人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
发明人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/78 , H01L29/7851 , H01L29/792
摘要： A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.
摘要翻译：非易失性存储器件防止电荷扩展。非易失性存储器件包括半导体衬底中的隔离沟槽，隔离层部分地填充由隔离沟槽限定的第一和第二鳍片之间的隔离沟槽，跨越第一鳍片和第二鳍片的控制栅极电极，第一电荷陷阱图案在第一鳍片和控制栅电极之间，以及第二鳍片和控制栅电极之间的第二电荷陷阱图案。

3. 发明授权

US07951671B2 Method of fabricating non-volatile memory device having separate charge trap patterns 失效
标题翻译：制造具有单独的电荷陷阱图案的非易失性存储器件的方法
公开(公告)号：US07951671B2
公开(公告)日：2011-05-31
申请号：US12453419
申请日：2009-05-11
申请人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
发明人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/78 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a non-volatile memory device includes forming an isolation trench in a semiconductor substrate, and the isolation trench defines first and second fins. The method further includes forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.
摘要翻译：一种制造非易失性存储器件的方法包括在半导体衬底中形成隔离沟槽，隔离沟槽限定第一和第二鳍片。该方法还包括形成部分地填充隔离沟槽的隔离层，分别形成分别覆盖从隔离层突出的第一和第二鳍片的部分的第一和第二电荷陷阱图案，以及形成覆盖第一和第二电荷陷阱图案的控制栅电极并穿过第一和第二鳍片。

4. 发明申请

US20080207503A1 Composition and Treatment Methods for Coronary Artery Disease 审中-公开
标题翻译：冠状动脉疾病的组成和治疗方法
公开(公告)号：US20080207503A1
公开(公告)日：2008-08-28
申请号：US11722664
申请日：2005-12-22
申请人： Byung-Hong Chung , Byung Hui Cho
发明人： Byung-Hong Chung , Byung Hui Cho
IPC分类号： A61K38/12 , A61K31/685 , A61P9/10
CPC分类号： A61K38/12 , A61K31/685
摘要： The present disclosure demonstrates that cholesterol-free discoidal reconstituted HDL (R-HDL), phosphatidyl-choline (PC) and PC liposomes effectively released cholesterol from ICP. Native HDL and its apolipoproteins were not able to release cholesterol from ICP. The release of ICP cholesterol by R-HDL was dose-dependent and accompanied by the transfer of >8× more PC in the reverse direction (i.e., from R-HDL to ICP), resulting in a marked enrichment of ICP with PC. The enrichment of ICP with PC resulted in the dissolution of cholesterol crystals on ICP and allowed the removal of ICP cholesterol by apo HDL and plasma. The present disclosure provides a method of treatment for removal of cholesterol from ICP in vivo and compositions for use in such method of treatment. Such methods may be used in the treatment and/or prevention of atherosclerosis, coronary artery disease, and related disease states and conditions.
摘要翻译：本公开内容表明，无胆固醇的盘状重组HDL（R-HDL），磷脂酰胆碱（PC）和PC脂质体有效地从ICP中释放胆固醇。天然HDL及其载脂蛋白不能从ICP中释放胆固醇。通过R-HDL释放ICP胆固醇是剂量依赖性的，并且伴随着相反方向（即，从R-HDL到ICP）转移> 8x个更多的PC，导致ICP与PC的显着浓缩。 ICP与PC的富集导致胆固醇晶体在ICP上的溶解，并允许通过载脂蛋白HDL和血浆去除ICP胆固醇。本公开提供了一种用于从体内从ICP中除去胆固醇的方法和用于这种治疗方法的组合物。这些方法可用于治疗和/或预防动脉粥样硬化，冠状动脉疾病和相关疾病状态和病症。

5. 发明申请

US20070111441A1 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070111441A1
公开(公告)日：2007-05-17
申请号：US11594808
申请日：2006-11-09
申请人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
发明人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。中间栅极图案和上部栅极图案之间的边界可以具有圆角。

6. 发明授权

US08642458B2 Method of fabricating nonvolatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08642458B2
公开(公告)日：2014-02-04
申请号：US13414085
申请日：2012-03-07
申请人： Byung-Hong Chung , Young-Hee Kim , In-Sun Yi , Han-Mei Choi
发明人： Byung-Hong Chung , Young-Hee Kim , In-Sun Yi , Han-Mei Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76883 , H01L21/28273 , H01L21/32115 , H01L21/76882 , H01L27/11521 , H01L29/66825
摘要： A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.
摘要翻译：一种制造非易失性存储器件的方法包括提供一种中间结构，其中在半导体衬底上相邻设置浮置栅极和隔离膜，并且栅极绝缘膜设置在浮置栅极和隔离膜上，形成导电膜，并且使导电膜退火，使得浮栅的上部的导电膜的一部分向下流到浮栅的下部和隔离膜的上部。

7. 发明授权

US06593190B2 Non-volatile memory device having a bit line contact pad and method for manufacturing the same 有权
公开(公告)号：US06593190B2
公开(公告)日：2003-07-15
申请号：US10072577
申请日：2002-02-06
申请人： Seung-Min Lee , Byung-Hong Chung
发明人： Seung-Min Lee , Byung-Hong Chung
IPC分类号： H01L21336
CPC分类号： H01L21/76895 , H01L27/115 , H01L27/11521
摘要： A non-volatile memory device and a method for manufacturing the same are disclosed. A non-volatile memory device comprises a semiconductor substrate having active areas which extend in a first direction and are repeatedly arranged in a second direction orthogonal to the first direction, a plurality of word lines formed on the semiconductor substrate which extending in the second direction while being repeatedly arranged in the first direction, string select lines adjacent to a first word line and extending in the second direction, ground select lines adjacent to a last word line and extending in the second direction, a first insulating interlayer formed on the resultant structure and comprising a first opening exposing the active area between the ground select lines and a second opening exposing the active area between the string select lines, a bit line contact pad formed in the second opening. A sidewall of the contact pad comprises a negative slope in the first direction and a positive slope in the second direction. A hard mask layer pattern, having the same pattern size as the active area, is formed on the contact pad and the first insulating interlayer. A second insulating interlayer is formed on the hard mask layer pattern and the first insulating interlayer. The second insulating interlayer has a bit line contact hole on the contact pad and thus the process margin is sufficiently achieved.

8. 发明申请

US20090004826A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090004826A1
公开(公告)日：2009-01-01
申请号：US12214019
申请日：2008-06-16
申请人： Young-Hoo Kim , Hyun Park , Byung-Hong Chung , Jeong-Lim Nam
发明人： Young-Hoo Kim , Hyun Park , Byung-Hong Chung , Jeong-Lim Nam
IPC分类号： H01L21/20
CPC分类号： H01L27/11568 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11551
摘要： In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.
摘要翻译：在制造半导体器件的方法中，提供分别包括多个存储单元和选择晶体管的第一衬底和第二衬底。分别在第一基板和第二基板上形成第一绝缘层和第二绝缘中间层，以覆盖存储单元和选择晶体管。部分地去除第二基板的下表面以减小第二基板的厚度。第二基板的下表面附接到第一绝缘中间层。插塞通过第二绝缘中间层，第二基板和第一绝缘夹层形成，以将第一基板和第二基板中的选择晶体管电连接到插头。因此，在热处理过程中，第一衬底中的杂质离子将不会扩散。

9. 发明授权

US07250346B2 Dual gate oxide structure in semiconductor device and method thereof 失效
标题翻译：半导体器件中的双栅极氧化物结构及其方法
公开(公告)号：US07250346B2
公开(公告)日：2007-07-31
申请号：US10876277
申请日：2004-06-23
申请人： Jong-Sik Chun , Hyun-Ho Jo , Byung-Hong Chung
发明人： Jong-Sik Chun , Hyun-Ho Jo , Byung-Hong Chung
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823462
摘要： In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.
摘要翻译：在制造半导体器件的双栅氧化层的方法中，其具有在半导体衬底上以相互不同的电压工作的第一和第二有源区，所述第一和第二有源区具有STI（浅沟槽隔离）的器件隔离层，结构体; 制造双栅极绝缘层的方法包括：在形成与第一和第二有源区的上表面相对应的栅绝缘层之前，形成器件隔离层，使其最上部位于第一和第二有源区的上表面下方，第二活跃区域。由此，直到用作有源区域的沟槽侧壁的一部分为止，增加有源区域的单元电流并且防止由有源区域和场区域之间的阶梯式覆盖引起的桁条以及由活动区域和场区域之间的边界面。

10. 发明授权

US06914013B2 Method of forming semiconductor device containing oxide/nitride/oxide dielectric layer 有权
标题翻译：形成含有氧化物/氮化物/氧化物介电层的半导体器件的方法
公开(公告)号：US06914013B2
公开(公告)日：2005-07-05
申请号：US10431609
申请日：2003-05-08
申请人： Byung-Hong Chung
发明人： Byung-Hong Chung
IPC分类号： H01L21/8247 , H01L21/31 , H01L21/318 , H01L21/76 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , H01L21/336 , H01L21/469
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/511
摘要： A semiconductor device and a method of forming the semiconductor device are disclosed. The semiconductor device includes: a semiconductor substrate; a patterned floating gate formed on the semiconductor substrate, the patterned floating gate having upper and side parts and corners; and a dielectric layer containing a first oxide layer, a nitride layer and a second oxide layer deposited over the semiconductor substrate and the floating gate. The ratio of the thickness of the first oxide layer in the upper and side parts of the patterned floating gate to the thickness of the first oxide layer in the corners of the patterned floating gate does not exceed 1.4. The semiconductor device has an improved coupling coefficient, and reduced leakage current.
摘要翻译：公开了半导体器件和形成半导体器件的方法。半导体器件包括：半导体衬底; 形成在所述半导体衬底上的图案化浮栅，所述图案化浮栅具有上部和侧部和拐角; 以及包含沉积在半导体衬底和浮动栅极上的第一氧化物层，氮化物层和第二氧化物层的电介质层。图案化浮栅的上部和侧部中的第一氧化物层的厚度与图案化浮栅的角部中的第一氧化物层的厚度之比不超过1.4。该半导体器件具有改善的耦合系数，并减少漏电流。

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