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1. 发明申请

US20050085042A1 Dual gate oxide structure in semiconductor device and method thereof 失效
标题翻译：半导体器件中的双栅极氧化物结构及其方法
公开(公告)号：US20050085042A1
公开(公告)日：2005-04-21
申请号：US10876277
申请日：2004-06-23
申请人： Jong-Sik Chun , Hyun-Ho Jo , Byung-Hong Chung
发明人： Jong-Sik Chun , Hyun-Ho Jo , Byung-Hong Chung
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/00 , H01L21/84
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823462
摘要： In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.
摘要翻译：在制造半导体器件的双栅氧化层的方法中，其具有在半导体衬底上以相互不同的电压工作的第一和第二有源区，所述第一和第二有源区具有STI（浅沟槽隔离）的器件隔离层，结构体; 制造双栅极绝缘层的方法包括：在形成与第一和第二有源区的上表面相对应的栅绝缘层之前，形成器件隔离层，使其最上部位于第一和第二有源区的上表面下方，第二活跃区域。由此，直到用作有源区域的沟槽侧壁的一部分为止，增加有源区域的单元电流并且防止由有源区域和场区域之间的阶梯式覆盖引起的纵梁以及由活动区域和场区域之间的边界面。

2. 发明授权

US07250346B2 Dual gate oxide structure in semiconductor device and method thereof 失效
标题翻译：半导体器件中的双栅极氧化物结构及其方法
公开(公告)号：US07250346B2
公开(公告)日：2007-07-31
申请号：US10876277
申请日：2004-06-23
申请人： Jong-Sik Chun , Hyun-Ho Jo , Byung-Hong Chung
发明人： Jong-Sik Chun , Hyun-Ho Jo , Byung-Hong Chung
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823462
摘要： In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.
摘要翻译：在制造半导体器件的双栅氧化层的方法中，其具有在半导体衬底上以相互不同的电压工作的第一和第二有源区，所述第一和第二有源区具有STI（浅沟槽隔离）的器件隔离层，结构体; 制造双栅极绝缘层的方法包括：在形成与第一和第二有源区的上表面相对应的栅绝缘层之前，形成器件隔离层，使其最上部位于第一和第二有源区的上表面下方，第二活跃区域。由此，直到用作有源区域的沟槽侧壁的一部分为止，增加有源区域的单元电流并且防止由有源区域和场区域之间的阶梯式覆盖引起的桁条以及由活动区域和场区域之间的边界面。

3. 发明授权

US06673718B1 Methods for forming aluminum metal wirings 有权
标题翻译：铝金属布线形成方法
公开(公告)号：US06673718B1
公开(公告)日：2004-01-06
申请号：US10305244
申请日：2002-11-27
申请人： Jong-Myeong Lee , In-Sun Park , Hyeon-Deok Lee , Jong-Sik Chun
发明人： Jong-Myeong Lee , In-Sun Park , Hyeon-Deok Lee , Jong-Sik Chun
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76879 , H01L21/76882 , H01L2221/1089
摘要： An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.
摘要翻译：在基板的接触孔或凹槽内选择性地形成铝布线。包含氮的中间层形成在基板的主表面上并在接触孔或凹槽的内表面上方。用等离子体处理位于基板的主表面上方的中间层的第一表面部分，以在中间层的第一表面部分处形成被动层。然后，没有中间真空断裂，铝膜仅沉积在中间层的位于接触孔或凹槽的内表面上方的第二表面部分上。中间层的第一表面部分的等离子体处理防止铝膜在中间层的第一表面部分上的CAD沉积。

4. 发明授权

US06905960B2 Method of forming a contact in a semiconductor device 失效
标题翻译：在半导体器件中形成接触的方法
公开(公告)号：US06905960B2
公开(公告)日：2005-06-14
申请号：US10657140
申请日：2003-09-09
申请人： Hong-Mi Park , Jong-Sik Chun , Hyeon-Deok Lee , In-Sun Park , Jong-Myeong Lee , Ju-Cheol Shin
发明人： Hong-Mi Park , Jong-Sik Chun , Hyeon-Deok Lee , In-Sun Park , Jong-Myeong Lee , Ju-Cheol Shin
IPC分类号： H01L21/28 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76843 , H01L21/76871
摘要： In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.
摘要翻译：在半导体器件中形成接触的方法中，在半导体衬底上形成绝缘层。然后，通过选择性地蚀刻绝缘层形成接触孔。阻挡金属层沉积在接触孔的侧表面和底表面上，并且在绝缘层的顶表面上沉积到均匀的厚度。在阻挡金属层上沉积抗氧化金属材料的润湿层。在润湿层上形成金属层，并填充接触孔，从而在半导体器件中形成接触。

5. 发明申请

US20050035458A1 Metal film semiconductor device and a method for forming the same 审中-公开
公开(公告)号：US20050035458A1
公开(公告)日：2005-02-17
申请号：US10945992
申请日：2004-09-22
申请人： Jong-Myeong Lee , In-Sun Park , Jong-Sik Chun
发明人： Jong-Myeong Lee , In-Sun Park , Jong-Sik Chun
IPC分类号： C23C16/20 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76888 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53223 , H01L2221/1089 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for forming a metal film including forming a metal barrier layer on a surface of a substrate, on a bottom surface of a recess and on sidewalls of the recess, forming a first metal film on the substrate but not in the recess, treating the first metal film with nitrogen plasma to form an insulation film including nitrogen, forming a second metal film on a portion of the metal barrier layer in the recess, and forming a third metal film on the substrate, the recess and the insulation film.

6. 发明授权

US06844627B2 Metal film semiconductor device and a method for forming the same 有权
标题翻译：金属膜半导体器件及其形成方法
公开(公告)号：US06844627B2
公开(公告)日：2005-01-18
申请号：US10367916
申请日：2003-02-19
申请人： Jong-Myeong Lee , In-Sun Park , Jong-Sik Chun
发明人： Jong-Myeong Lee , In-Sun Park , Jong-Sik Chun
IPC分类号： C23C16/20 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76888 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53223 , H01L2221/1089 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for forming a metal film including forming a metal barrier layer on a surface of a substrate, on a bottom surface of a recess and on sidewalls of the recess, forming a first metal film on the substrate but not in the recess, treating the first metal film with nitrogen plasma to form an insulation film including nitrogen, forming a second metal film on a portion of the metal barrier layer in the recess, and forming a third metal film on the substrate, the recess and the insulation film.
摘要翻译：一种用于形成金属膜的方法，包括在基板的表面上，在凹部的底表面和凹部的侧壁上形成金属阻挡层，在基板上形成第一金属膜而不在凹部中，具有氮等离子体的第一金属膜以形成包括氮的绝缘膜，在所述凹部中的所述金属阻挡层的一部分上形成第二金属膜，并在所述基板，所述凹部和所述绝缘膜上形成第三金属膜。

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