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1. 发明授权

US08623458B2 Methods of directed self-assembly, and layered structures formed therefrom 有权
标题翻译：定向自组装的方法和由其形成的分层结构
公开(公告)号：US08623458B2
公开(公告)日：2014-01-07
申请号：US12642018
申请日：2009-12-18
申请人： Joy Cheng , Matthew E. Colburn , Stefan Harrer , William D. Hinsberg , Steven J. Holmes , Ho-Cheol Kim , Daniel Paul Sanders
发明人： Joy Cheng , Matthew E. Colburn , Stefan Harrer , William D. Hinsberg , Steven J. Holmes , Ho-Cheol Kim , Daniel Paul Sanders
IPC分类号： B81C1/00 , C08J5/18 , C08J5/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： A layered structure comprising a self-assembled material is formed by a method that includes forming a photochemically, thermally and/or chemically treated patterned photoresist layer disposed on a first surface of a substrate. The treated patterned photoresist layer comprises a non-crosslinked treated photoresist. An orientation control material is cast on the treated patterned photoresist layer, forming a layer containing orientation control material bound to a second surface of the substrate. The treated photoresist and, optionally, any non-bound orientation control material are removed by a development process, resulting in a pre-pattern for self-assembly. A material capable of self-assembly is cast on the pre-pattern. The casted material is allowed to self-assemble with optional heating and/or annealing to produce the layered structure.
摘要翻译：包括自组装材料的层状结构通过包括形成设置在衬底的第一表面上的光化学，热和/或化学处理的图案化光致抗蚀剂层的方法形成。经处理的图案化光刻胶层包括非交联处理的光致抗蚀剂。将取向控制材料浇铸在经处理的图案化的光致抗蚀剂层上，形成包含与基材的第二表面结合的取向控制材料的层。经处理的光致抗蚀剂和任选的任何未结合的取向控制材料通过显影过程被去除，从而形成用于自组装的预图案。能够自组装的材料在预制图案上铸造。允许铸造材料通过任选的加热和/或退火自组装以产生分层结构。

2. 发明申请

US20110204523A1 METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL MULTIPLE EXPOSURE PATTERNING SCHEME 有权
标题翻译：使用多次多次曝光方案制作双重结构结构的方法
公开(公告)号：US20110204523A1
公开(公告)日：2011-08-25
申请号：US12708877
申请日：2010-02-19
申请人： John C. Arnold , Kuang-Jung Chen , Matthew E. Colburn , Dario L. Goldfarb , Stefan Harrer , Steven J. Holmes , Pushkara Varanasi
发明人： John C. Arnold , Kuang-Jung Chen , Matthew E. Colburn , Dario L. Goldfarb , Stefan Harrer , Steven J. Holmes , Pushkara Varanasi
IPC分类号： H01L23/522 , G03F7/20
CPC分类号： H01L23/53295 , G03F7/091 , G03F7/38 , H01L21/0274 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1021 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.
摘要翻译：一种用于制造双镶嵌结构的方法包括提供涂覆在下面的电介质堆叠上的第一光致抗蚀剂层，将所述第一光致抗蚀剂层暴露于第一预定图案的光，将第二光致抗蚀剂层涂覆到预曝光的第一光致抗蚀剂层上，第二光致抗蚀剂层到第二预定图案的光，任选地后曝光烘烤多层光致抗蚀剂层并显影所述光致抗蚀剂层以在光致抗蚀剂层中形成多层双镶嵌结构。

3. 发明授权

US08536031B2 Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme 有权
公开(公告)号：US08536031B2
公开(公告)日：2013-09-17
申请号：US12708877
申请日：2010-02-19
申请人： John C. Arnold , Kuang-Jung Chen , Matthew E. Colburn , Dario L. Goldfarb , Stefan Harrer , Steven J. Holmes , Pushkara Varanasi
发明人： John C. Arnold , Kuang-Jung Chen , Matthew E. Colburn , Dario L. Goldfarb , Stefan Harrer , Steven J. Holmes , Pushkara Varanasi
IPC分类号： H01L21/26 , H01L21/42
CPC分类号： H01L23/53295 , G03F7/091 , G03F7/38 , H01L21/0274 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1021 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.

4. 发明申请

US20120126358A1 TONE INVERSION WITH PARTIAL UNDERLAYER ETCH 失效
标题翻译：带有部分底层蚀刻的色调
公开(公告)号：US20120126358A1
公开(公告)日：2012-05-24
申请号：US12952248
申请日：2010-11-23
申请人： John C. Arnold , Sean D. Burns , Matthew E. Colburn , Steven J. Holmes , Yunpeng Yin
发明人： John C. Arnold , Sean D. Burns , Matthew E. Colburn , Steven J. Holmes , Yunpeng Yin
IPC分类号： H01L21/311 , H01L23/00 , H01L21/768
CPC分类号： H01L23/00 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.
摘要翻译：用于集成电路制造的色调反转的方法包括：在衬底的顶部上提供具有底层的衬底; 产生第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露位于所述底层下方的所述基板; 用一层图像反向材料（IRM）覆盖第一个图案; 并将第二图案刻蚀成衬底。用于集成电路制造的色调反转的结构包括：衬底; 部分蚀刻的底层包括位于所述衬底上方的第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露底层位于底层下方; 以及位于部分蚀刻的底层上方的图像反转材料（IRM）层。

5. 发明申请

US20110049680A1 DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS 有权
标题翻译：双重接触跟踪只能分离分离过程
公开(公告)号：US20110049680A1
公开(公告)日：2011-03-03
申请号：US12551801
申请日：2009-09-01
申请人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
发明人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
IPC分类号： H01L29/06 , G03F7/20 , H01L21/461
CPC分类号： H01L21/31144 , G03F7/0035 , H01L21/0271 , H01L21/0338
摘要： An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.
摘要翻译：集成电路形成为具有比这种结构的横向尺寸更紧密地在一起的结构，例如用于通过暗场分割俯仰技术以最小可光滑分辨尺寸形成的电子元件的接触。对于需要蚀刻多个顺序施加的和图案化的抗蚀剂层中的每一个的硬标记的分割间距处理的可接受的覆盖精度和处理效率和处理量通过使用酸敏感的硬标记材料和通过抗蚀剂中的图案化孔接触硬掩模的区域的酸性外涂层。通过烘烤酸性外涂层来激活硬掩模的接触区域以进行显影。

6. 发明授权

US08053368B2 Method for removing residues from a patterned substrate 失效
标题翻译：从图案化衬底去除残留物的方法
公开(公告)号：US08053368B2
公开(公告)日：2011-11-08
申请号：US12055648
申请日：2008-03-26
申请人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
发明人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
IPC分类号： H01L21/311
CPC分类号： H01L21/0276 , G03F7/091 , G03F7/40
摘要： The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer.
摘要翻译：本发明涉及一种用于从图案化衬底的开放区域去除残留物的方法，包括以下步骤：在衬底上提供可显影抗反射涂层（DBARC）的层; 在所述DBARC层上提供一层光致抗蚀剂; 将所述光致抗蚀剂层和所述DBARC层图案化地曝光到辐射; 用第一显影剂显影所述光致抗蚀剂层和所述DBARC层以在所述光致抗蚀剂和DBARC层中形成图案化结构; 在所述图案化结构上沉积一层显影剂可溶性材料; 并用第二显影剂除去所述显影剂可溶性材料。

7. 发明申请

US20090246958A1 METHOD FOR REMOVING RESIDUES FROM A PATTERNED SUBSTRATE 失效
标题翻译：从图案基板上移除残留物的方法
公开(公告)号：US20090246958A1
公开(公告)日：2009-10-01
申请号：US12055648
申请日：2008-03-26
申请人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
发明人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
IPC分类号： H01L21/311
CPC分类号： H01L21/0276 , G03F7/091 , G03F7/40
摘要： The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer.
摘要翻译：本发明涉及一种用于从图案化衬底的开放区域去除残留物的方法，包括以下步骤：在衬底上提供可显影抗反射涂层（DBARC）的层; 在所述DBARC层上提供一层光致抗蚀剂; 将所述光致抗蚀剂层和所述DBARC层图案化地曝光到辐射; 用第一显影剂显影所述光致抗蚀剂层和所述DBARC层以在所述光致抗蚀剂和DBARC层中形成图案化结构; 在所述图案化结构上沉积一层显影剂可溶性材料; 并用第二显影剂除去所述显影剂可溶性材料。

8. 发明授权

US08470711B2 Tone inversion with partial underlayer etch for semiconductor device formation 失效
标题翻译：用于半导体器件形成的部分底层蚀刻的色调反演
公开(公告)号：US08470711B2
公开(公告)日：2013-06-25
申请号：US12952248
申请日：2010-11-23
申请人： John C. Arnold , Sean D. Burns , Matthew E. Colburn , Steven J. Holmes , Yunpeng Yin
发明人： John C. Arnold , Sean D. Burns , Matthew E. Colburn , Steven J. Holmes , Yunpeng Yin
IPC分类号： H01L21/44
CPC分类号： H01L23/00 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.
摘要翻译：用于集成电路制造的色调反转的方法包括：在衬底的顶部上提供具有底层的衬底; 产生第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露位于所述底层下方的所述基板; 用一层图像反向材料（IRM）覆盖第一个图案; 并将第二图案刻蚀成衬底。用于集成电路制造的色调反转的结构包括：衬底; 部分蚀刻的底层包括位于所述衬底上方的第一图案，所述第一图案被部分蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露底层位于底层下方; 以及位于部分蚀刻的底层上方的图像反转材料（IRM）层。

9. 发明申请

US20130026639A1 Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme 审中-公开
标题翻译：使用多级多重曝光图案化方案制造双镶嵌结构的方法
公开(公告)号：US20130026639A1
公开(公告)日：2013-01-31
申请号：US13615980
申请日：2012-09-14
申请人： John C. Arnold , Kuang-Jung Chen , Matthew E. Colburn , Dario L. Goldfarb , Stefan Harrar , Steven J. Holmes , Pushkara Varanasi
发明人： John C. Arnold , Kuang-Jung Chen , Matthew E. Colburn , Dario L. Goldfarb , Stefan Harrar , Steven J. Holmes , Pushkara Varanasi
IPC分类号： H01L21/428 , H01L23/48
CPC分类号： H01L23/53295 , G03F7/091 , G03F7/38 , H01L21/0274 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1021 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.
摘要翻译：一种用于制造双镶嵌结构的方法包括提供涂覆在下面的电介质堆叠上的第一光致抗蚀剂层，将所述第一光致抗蚀剂层暴露于第一预定图案的光，将第二光致抗蚀剂层涂覆到预曝光的第一光致抗蚀剂层上，第二光致抗蚀剂层到第二预定图案的光，任选地后曝光烘烤多层光致抗蚀剂层并显影所述光致抗蚀剂层以在光致抗蚀剂层中形成多层双镶嵌结构。

10. 发明授权

US07994060B2 Dual exposure track only pitch split process 有权
标题翻译：双曝光轨道只有音高分割过程
公开(公告)号：US07994060B2
公开(公告)日：2011-08-09
申请号：US12551801
申请日：2009-09-01
申请人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
发明人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
IPC分类号： H01L21/311 , H01L21/469
CPC分类号： H01L21/31144 , G03F7/0035 , H01L21/0271 , H01L21/0338
摘要： An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.
摘要翻译：集成电路形成为具有比这种结构的横向尺寸更紧密地在一起的结构，例如用于通过暗场分割俯仰技术以最小可光滑分辨尺寸形成的电子元件的接触。对于需要蚀刻多个顺序施加的和图案化的抗蚀剂层中的每一个的硬标记的分割间距处理的可接受的覆盖精度和处理效率和处理量通过使用酸敏感的硬标记材料和通过抗蚀剂中的图案化孔接触硬掩模的区域的酸性外涂层。通过烘烤酸性外涂层来激活硬掩模的接触区域以进行显影。

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