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1. 发明授权

US08024141B2 Test and measurement instrument and method for providing post-acquisition trigger control and presentation 失效
标题翻译：用于提供采集后触发控制和演示的测试和测量仪器和方法
公开(公告)号：US08024141B2
公开(公告)日：2011-09-20
申请号：US12576045
申请日：2009-10-08
申请人： Josiah A. Bartlett , Kristie L. Veith , Steven K. Sullivan
发明人： Josiah A. Bartlett , Kristie L. Veith , Steven K. Sullivan
IPC分类号： G01R13/02
CPC分类号： G01R13/0254 , G01R13/029
摘要： A test and measurement instrument and method for providing post-acquisition trigger control and presentation of associated waveforms on a display. An electrical signal under test is sampled and digitized, and stored in an acquisition memory as a data record. A display device draws a waveform associated with the signal under test. After the acquisition of the digital samples is stopped, a user selects trigger criteria using trigger controls such as a trigger level control. A trigger circuit detects a post-acquisition trigger event in the data record based on the trigger criteria causing an automatic adjustment of the waveform to conform to a time of the post-acquisition trigger event. One or more configurable trigger controls can be used to adjust a display of post-acquisition trigger events and waveforms. Upon resumption of the live-acquisition of data, the live waveform conforms to the newly selected trigger criteria as previewed during the post-acquisition mode.
摘要翻译：一种用于在显示器上提供采集后触发控制和显示相关波形的测试和测量仪器和方法。被测电信号被采样和数字化，并作为数据记录存储在采集存储器中。显示设备绘制与被测信号相关联的波形。在数字采样的采集停止之后，用户使用诸如触发电平控制的触发控制来选择触发条件。触发电路基于触发标准来检测数据记录中的采集后触发事件，导致波形的自动调整以符合采集后触发事件的时间。可以使用一个或多个可配置的触发控制来调整采集后触发事件和波形的显示。在恢复数据的实时采集之后，实时波形符合在采集后模式下预览的新选择的触发条件。

2. 发明授权

US08374811B2 High waveform throughput with a large acquisition memory 有权
标题翻译：具有大的采集存储器的高波形吞吐量
公开(公告)号：US08374811B2
公开(公告)日：2013-02-12
申请号：US12631968
申请日：2009-12-07
申请人： Steven K. Sullivan , Kristie L. Veith , Terrance R. Beale , Paul M. Gerlach , Gregory A. Martin , George S. Walker
发明人： Steven K. Sullivan , Kristie L. Veith , Terrance R. Beale , Paul M. Gerlach , Gregory A. Martin , George S. Walker
IPC分类号： G06F19/00 , G01R13/02
CPC分类号： G01R13/0236 , G01R13/0254
摘要： A waveform display apparatus and method displays one or more waveforms of a signal under test at high throughput while acquiring digital data of the signal under test in a large acquisition memory. A user sets a time interval of user's interest when viewing a signal under test and sets trigger criteria through a user interface. An ADC converts the signal under test into digital data that is stored in a large acquisition memory. A trigger unit detects and produces trigger events, based on a trigger, as trigger event information during one acquisition process. A trigger event eliminator may discard some of the trigger events based on pre-trigger and post-conditions set through the interface by a user. The trigger events are recorded in a trigger list as the trigger event information. A control unit locates the digital data in the acquisition memory corresponding to the trigger events in the trigger list and displays a waveform associated with the trigger event for the time interval on a display device.
摘要翻译：波形显示装置和方法以高吞吐量显示被测信号的一个或多个波形，同时在大的采集存储器中获取待测信号的数字数据。用户在查看被测信号时设置用户兴趣的时间间隔，并通过用户界面设置触发条件。 ADC将被测信号转换为存储在大型采集存储器中的数字数据。触发单元在一次采集过程中，根据触发信号检测并产生触发事件作为触发事件信息。触发事件消除器可以基于用户通过接口设置的预触发和后置条件来丢弃一些触发事件。触发事件记录在触发列表中作为触发事件信息。控制单元将对应于触发列表中的触发事件的采集存储器中的数字数据定位在显示设备上，并且在时间间隔上显示与触发事件相关联的波形。

3. 发明授权

US07558936B2 Data management in long record length memory 失效
标题翻译：长记录长度内存中的数据管理
公开(公告)号：US07558936B2
公开(公告)日：2009-07-07
申请号：US11388926
申请日：2006-03-24
申请人： Terrance R. Beale , Steven K. Sullivan , Kristie L. Veith
发明人： Terrance R. Beale , Steven K. Sullivan , Kristie L. Veith
IPC分类号： G06F12/00
CPC分类号： G06F5/14 , G01R13/029
摘要： A data management method for a long record length memory that is used for data acquisition writes data samples into an initial circular buffer within the memory having a size equal to a pre-trigger time. When a first trigger event occurs, the data samples are then written into a linear region after the circular buffer within the memory. The data sample acquisition in the linear region continues until a post-trigger and new pre-trigger time have elapsed after a last trigger event, at which point the acquisition terminates and the new pre-trigger time becomes a new circular buffer for a next trigger event. In this way all trigger events are captured with associated pre-trigger and post-trigger data.
摘要翻译：用于数据采集的长记录长度存储器的数据管理方法将数据样本写入具有等于预触发时间的大小的存储器内的初始循环缓冲器。当发生第一触发事件时，数据样本然后被写入存储器中的循环缓冲器之后的线性区域。线性区域中的数据样本采集继续，直到最后一次触发事件发生后触发和新的预触发时间，此时采集终止，新的预触发时间成为新的循环缓冲区，用于下一个触发事件。以这种方式，所有触发事件都将被捕获与相关的预触发和后触发数据。

4. 发明申请

US20140055480A1 TRIGGER DISPLAY 审中-公开
标题翻译：触发显示
公开(公告)号：US20140055480A1
公开(公告)日：2014-02-27
申请号：US13593275
申请日：2012-08-23
申请人： Steven K. Sullivan , Kristie L. Veith , Shane L. Arnold
发明人： Steven K. Sullivan , Kristie L. Veith , Shane L. Arnold
IPC分类号： G06T11/00
CPC分类号： G06T11/001 , G01R13/0254 , G01R13/029
摘要： Embodiments of the invention include an apparatus and method for displaying trigger frequency on a display of a test and measurement instrument. During each of a series of equal time intervals, a number of trigger events are counted. Each trigger event count is associated with a corresponding logical column of a trigger display window. The trigger event counts are written to memory locations associated with the corresponding logical columns of the trigger display window. Trigger frequency logic generates multiple trigger frequency indicators based on the trigger event counts. The trigger frequency indicators are displayed in the trigger display window to quickly and efficiently convey trigger density information to a user of the test and measurement instrument. The apparatus includes jitter reduction logic to reduce or eliminate unwanted jitter related to the trigger frequency indicators.
摘要翻译：本发明的实施例包括用于在测试和测量仪器的显示器上显示触发频率的装置和方法。在一系列相等的时间间隔的每一个期间，对多个触发事件进行计数。每个触发事件计数与触发显示窗口的对应逻辑列相关联。触发事件计数被写入与触发显示窗口的相应逻辑列相关联的存储器位置。触发频率逻辑根据触发事件计数产生多个触发频率指示。触发频率指示器显示在触发显示窗口中，以便快速有效地将触发密度信息传达给测试和测量仪器的用户。该装置包括用于减少或消除与触发频率指示器相关的不期望的抖动的抖动降低逻辑。

5. 发明授权

US07366628B2 Compressed logic sample storage 有权
标题翻译：压缩逻辑样本存储
公开(公告)号：US07366628B2
公开(公告)日：2008-04-29
申请号：US11266105
申请日：2005-11-02
申请人： Steven K. Sullivan , Kenneth P. Dobyns
发明人： Steven K. Sullivan , Kenneth P. Dobyns
IPC分类号： G06F19/00
CPC分类号： H03M7/3066 , G01R31/31921
摘要： A test and measurement Instrument samples an input digital logic signal to produce logic samples, compresses the logic samples into compression codes, and stores the compression codes into acquisition memory. Compression includes parsing the logic samples into groups and assigning compression codes to those groups, and is performed so as not to lose information about the input digital logic signal's activity. The instrument converts the stored compression codes into a waveform image in display memory and displays the stored waveform image on a display device.
摘要翻译：测试和测量仪器对输入数字逻辑信号进行采样以产生逻辑采样，将逻辑采样压缩为压缩代码，并将压缩代码存储到采集存储器中。压缩包括将逻辑样本分解成组并将压缩码分配给这些组，并且被执行以便不丢失关于输入数字逻辑信号的活动的信息。仪器将存储的压缩码转换为显示存储器中的波形图像，并将显示的存储的波形图像显示在显示设备上。

6. 发明授权

US06571185B1 Continually responsive and anticipating automatic setup function for a digital oscilloscope 失效
标题翻译：持续响应并预测数字示波器的自动设置功能
公开(公告)号：US06571185B1
公开(公告)日：2003-05-27
申请号：US09295070
申请日：1999-04-20
申请人： Michael A. Gauland , Steven K. Sullivan , Roy I. Siegel , Frederick A. Azinger , Charles L. Saxe
发明人： Michael A. Gauland , Steven K. Sullivan , Roy I. Siegel , Frederick A. Azinger , Charles L. Saxe
IPC分类号： G01R1302
CPC分类号： G01R13/02
摘要： Multiple views of the signal are generated by a time-sharing use of the oscilloscope's acquisition hardware. The instrument software makes a set of measurements of the input signal, and from the results of those measurements classifies the input signal as to type. Signals of particular types implicitly select suites of views of the signal. The operator sees examples of the other views available while a related view is the main view. Alternate views can be “live” miniature views, and displayed alongside in simplified form, alongside the main view. By clicking on them, these alternative views may be made to become the main view. The operator can add and modify views. Each view comes with a set of measurements that are automatically performed and the results are displayed on the screen as text annotation to the waveform. A different view of the signal comes with different automatic measurements, and presents the results of these measurements as annotations to the waveform image. These next alternative setups may be miniature “live” displays.
摘要翻译：信号的多个视图通过示波器采集硬件的分时使用产生。仪器软件对输入信号进行一组测量，并根据这些测量结果对输入信号进行分类。特定类型的信号隐含地选择信号的视图的套件。操作员可以看到可用的其他视图的示例，而相关视图是主视图。另外的视图可以是“活的”微型视图，并且以简化的形式显示在主视图的旁边。通过点击它们，可以将这些替代视图作为主视图。操作员可以添加和修改视图。每个视图都带有一组自动执行的测量结果，并将结果作为波形的文本注释显示在屏幕上。信号的不同视图带有不同的自动测量，并将这些测量的结果呈现为波形图像的注释。这些下一个替代设置可以是微型的“直播”显示器。

7. 发明授权

US5521599A High speed analog signal sampling system 失效
标题翻译：高速模拟信号采样系统
公开(公告)号：US5521599A
公开(公告)日：1996-05-28
申请号：US323178
申请日：1994-10-14
申请人： Benjamin J. McCarroll , Steven K. Sullivan
发明人： Benjamin J. McCarroll , Steven K. Sullivan
IPC分类号： G11C27/02 , H03M1/12
CPC分类号： G11C27/026
摘要： A high speed analog signal sampling system. The system comprises a timing chain having a plurality of delay elements arranged in series and a sample rate multiplier having a delay lock control system responsive to the outputs of first, second and third parallel delay elements in the sample rate multiplier to control the delay of the second parallel delay element so that its strobe signal output occurs one-half the time between the strobe signal outputs of the first parallel delay element and the third parallel delay element. The first, second and third parallel delay elements are the first three parallel delay elements of the timing chain, and a control signal of the delay lock control system is used to adjust and control the amount of delay introduced by every other parallel delay element after the second parallel delay element. The second and third parallel delay elements straddle one of the series delay elements in the timing chain, while the first parallel delay element has the same input as the second parallel delay element. The delay lock control system employs a sampling circuit which samples the strobe signal output of the first parallel delay element in response to an output of the second parallel delay element and which samples the strobe signal output of the second parallel delay element in response to an output of the third delay element, and further employs a control circuit which filters the difference between those two sampled output signals and provides that filtered difference as the control signal.
摘要翻译：高速模拟信号采样系统。该系统包括具有串联布置的多个延迟元件的定时链和具有响应于采样率倍增器中的第一，第二和第三并行延迟元件的输出的延迟锁定控制系统的采样率倍增器，以控制第二并行延迟元件，使得其选通信号输出发生在第一并行延迟元件的选通信号输出与第三并行延迟元件之间的一半时间。第一，第二和第三并行延迟元件是定时链的前三个并行延迟元件，并且延迟锁定控制系统的控制信号用于调整和控制由每个其它并行延迟元件引入的延迟量第二并行延迟元件。第二和第三并行延迟元件跨越定时链中的一个串联延迟元件，而第一并行延迟元件具有与第二并行延迟元件相同的输入。延迟锁定控制系统采用采样电路，该采样电路响应于第二并行延迟元件的输出对第一并行延迟元件的选通信号输出进行采样，并且响应于输出对第二并行延迟元件的选通信号输出进行采样并且进一步采用对这两个采样输出信号之间的差值进行滤波的控制电路，并提供该滤波差值作为控制信号。

8. 发明授权

US5144525A Analog acquisition system including a high speed timing generator 失效
标题翻译：模拟采集系统，包括高速时序发生器
公开(公告)号：US5144525A
公开(公告)日：1992-09-01
申请号：US589222
申请日：1990-09-27
申请人： Charles L. Saxe , Steven K. Sullivan , Grigory Kogan
发明人： Charles L. Saxe , Steven K. Sullivan , Grigory Kogan
IPC分类号： G11C27/00 , G11C27/02 , G11C27/04
CPC分类号： G11C27/024 , G11C27/04
摘要： An analog acquisition system includes an array of analog capture cells for capturing and storing a signal on an analog bus. Each capture cell in the array may be sequentially selected for sampling the signal at successive sample times. Timing for selecting a row of the analog memory array is provided by a slow shift register and timing for selecting a capture cell within the row of the analog memory array is provided by a fast tapped delay line. Additional circuitry is provided for controlling the delay of the tapped delay line such that total delay is equal to the time the slow shift register takes to transfer from one row to the next.

9. 发明授权

US07352167B2 Digital trigger 失效
标题翻译：数字触发
公开(公告)号：US07352167B2
公开(公告)日：2008-04-01
申请号：US11388925
申请日：2006-03-24
申请人： Steven K. Sullivan , Kristie Veith , Terrance R. Beale
发明人： Steven K. Sullivan , Kristie Veith , Terrance R. Beale
IPC分类号： G01R13/20
CPC分类号： G01R13/0254
摘要： An improved digital trigger circuit has a plurality of data samples extracted from an input electrical signal for each sample clock cycle. The plurality of data samples are compared in parallel with a high threshold level and a low threshold level which provides hysteresis for noise rejection. Also the plurality of data samples are used to determine sub-sample trigger positioning. The comparison outputs are input to a digital trigger logic circuit for identifying a selected trigger event and generating a trigger for the acquisition of data from the input electrical signal for analysis and display. The digital trigger logic provides edge event triggering, pulse width triggering and transition time triggering, among others.
摘要翻译：改进的数字触发电路具有从每个采样时钟周期的输入电信号提取的多个数据样本。将多个数据样本并行地与高阈值电平和低阈值电平进行比较，其提供用于噪声抑制的滞后。此外，多个数据样本用于确定子采样触发定位。比较输出被输入到数字触发逻辑电路，用于识别所选择的触发事件并产生用于从输入电信号中采集数据的触发用于分析和显示。数字触发逻辑提供边缘事件触发，脉冲宽度触发和转换时间触发等。

10. 发明授权

US06756876B2 Circuit interrupter and method 有权
标题翻译：电路断路器及方法
公开(公告)号：US06756876B2
公开(公告)日：2004-06-29
申请号：US10210688
申请日：2002-08-01
申请人： Steven K. Sullivan , Karl A. Kohm , Kevin R. French
发明人： Steven K. Sullivan , Karl A. Kohm , Kevin R. French
IPC分类号： H01H3752
CPC分类号： H01H37/5418 , H01H2037/5445
摘要： A current interrupter (10, 10′) includes bimetallic member (18) as a switching member having a formed portion (18a) providing snap action movement between oppositely dished configurations. An integrally formed extended length portion (18b) having a stiffening feature extends from the formed portion and mounts a movable contact at its free end. Stiffening feature embodiments include folded opposed marginal edges and one or more longitudinally extending ribs formed in the extended length portion. In one embodiment, the bimetallic member is cantilever mounted in a housing member (14). In another embodiment, a bimetallic member (18D) has first and second extended length portions (18b) extending from opposite sides of a formed portion to provide a circuit interrupter with a double break system.
摘要翻译：电流断流器（10,10'）包括作为切换构件的双金属构件（18），所述双金属构件具有形成部分（18a），其提供相对于碟形配置之间的快动作动运动。具有加强特征的整体形成的延伸长度部分（18b）从成形部分延伸并在其自由端安装可动触点。加强特征实施例包括折叠的相对的边缘和形成在延伸长度部分中的一个或多个纵向延伸的肋。在一个实施例中，双金属构件是悬臂安装在壳体构件（14）中。在另一个实施例中，双金属构件（18D）具有从形成部分的相对侧延伸的第一和第二延伸长度部分（18b），以提供具有双断裂系统的断路器。

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