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1. 发明申请

US20110137594A1 High Waveform Throughput with a Large Acquisition Memory 有权
标题翻译：具有大型采集存储器的高波形吞吐量
公开(公告)号：US20110137594A1
公开(公告)日：2011-06-09
申请号：US12631968
申请日：2009-12-07
申请人： Steven K. SULLIVAN , Kristie L. VEITH , Terrance R. BEALE , Paul M. GERLACH , Gregory A. MARTIN , George S. WALKER
发明人： Steven K. SULLIVAN , Kristie L. VEITH , Terrance R. BEALE , Paul M. GERLACH , Gregory A. MARTIN , George S. WALKER
IPC分类号： G01R13/02 , G06F19/00
CPC分类号： G01R13/0236 , G01R13/0254
摘要： A waveform display apparatus and method displays one or more waveforms of a signal under test at high throughput while acquiring digital data of the signal under test in a large acquisition memory. A user sets a time interval of user's interest when viewing a signal under test and sets trigger criteria through a user interface. An ADC converts the signal under test into digital data that is stored in a large acquisition memory. A trigger unit detects and produces trigger events, based on a trigger, as trigger event information during one acquisition process. A trigger event eliminator may discard some of the trigger events based on pre-trigger and post-conditions set through the interface by a user. The trigger events are recorded in a trigger list as the trigger event information. A control unit locates the digital data in the acquisition memory corresponding to the trigger events in the trigger list and displays a waveform associated with the trigger event for the time interval on a display device.
摘要翻译：波形显示装置和方法以高吞吐量显示被测信号的一个或多个波形，同时在大的采集存储器中获取待测信号的数字数据。用户在查看被测信号时设置用户兴趣的时间间隔，并通过用户界面设置触发条件。 ADC将被测信号转换为存储在大型采集存储器中的数字数据。触发单元在一次采集过程中，根据触发信号检测并产生触发事件作为触发事件信息。触发事件消除器可以基于用户通过接口设置的预触发和后置条件来丢弃一些触发事件。触发事件记录在触发列表中作为触发事件信息。控制单元将对应于触发列表中的触发事件的采集存储器中的数字数据定位在显示设备上，并且在时间间隔上显示与触发事件相关联的波形。

2. 发明申请

US20110060541A1 Test and Measurement Instrument and Method For Providing Post-Acquisition Trigger Control and Presentation 失效
公开(公告)号：US20110060541A1
公开(公告)日：2011-03-10
申请号：US12576045
申请日：2009-10-08
申请人： Josiah A. BARTLETT , Kristie L. VEITH , Steven K. SULLIVAN
发明人： Josiah A. BARTLETT , Kristie L. VEITH , Steven K. SULLIVAN
IPC分类号： G01R13/02
CPC分类号： G01R13/0254 , G01R13/029
摘要： A test and measurement instrument and method for providing post-acquisition trigger control and presentation of associated waveforms on a display. An electrical signal under test is sampled and digitized, and stored in an acquisition memory as a data record. A display device draws a waveform associated with the signal under test. After the acquisition of the digital samples is stopped, a user selects trigger criteria using trigger controls such as a trigger level control. A trigger circuit detects a post-acquisition trigger event in the data record based on the trigger criteria causing an automatic adjustment of the waveform to conform to a time of the post-acquisition trigger event. One or more configurable trigger controls can be used to adjust a display of post-acquisition trigger events and waveforms. Upon resumption of the live-acquisition of data, the live waveform conforms to the newly selected trigger criteria as previewed during the post-acquisition mode.

3. 发明授权

US07834780B2 Waveform compression and display 有权
标题翻译：波形压缩和显示
公开(公告)号：US07834780B2
公开(公告)日：2010-11-16
申请号：US11385170
申请日：2006-03-20
申请人： Steven K. Sullivan , Paul M. Gerlach , Kristie Veith , Kenneth P. Dobyns
发明人： Steven K. Sullivan , Paul M. Gerlach , Kristie Veith , Kenneth P. Dobyns
IPC分类号： H03M7/00
CPC分类号： G01R13/0272
摘要： A waveform compression and display technique saves both a peak detected version (background version) and a decimated/lowpass filtered version (foreground version) of a sampled electrical signal. The two versions are displayed simultaneously overlaid together in a contrasting manner so as not to obscure information contained in either of them. The lowpass filtered version uses a series of simple lowpass filters with decimation to produce a single data stream from a plurality of data streams derived from the sampled electrical signal. The single data stream may then be subjected to additional filtering, such as a cascaded integrator-comb filter, to obtain a desired frequency bandwidth. When displayed, the peak detect pixels adjacent the decimated/lowpass filtered pixels may be adjusted in intensity so that the low frequency information of the lowpass filtered waveform is not lost, while the peak detect pixels further from the lowpass filtered pixels are intensified to highlight the high frequency information. Alternatively the background version intensity may be controlled by a user control over a first range from zero to a predetermined maximum, and the foreground version may be controlled over a second range from a default intensity to a maximum, saturated intensity.
摘要翻译：波形压缩和显示技术节省了采样电信号的峰值检测版本（背景版本）和抽取/低通滤波版本（前景版本）。这两个版本以对比的方式同时叠加在一起，以免遮蔽其中任何一个中的信息。低通滤波器版本使用一系列具有抽取的简单低通滤波器，以从采样的电信号导出的多个数据流产生单个数据流。然后可以对单个数据流进行额外的滤波，例如级联的积分器梳状滤波器，以获得期望的频率带宽。当显示时，与抽取/低通滤波的像素相邻的峰值检测像素的强度可以被调整，使得低通滤波波形的低频信息不会丢失，而从低通滤波像素进一步增加峰值，从而突出显示高频信息。或者，背景版本强度可以由用户在从零到预定最大值的范围内的控制来控制，并且可以在从默认强度到最大饱和强度的第二范围内控制前景版本。

4. 发明授权

US07652465B2 No dead time data acquisition 失效
标题翻译：无死区数据采集
公开(公告)号：US07652465B2
公开(公告)日：2010-01-26
申请号：US11388428
申请日：2006-03-24
申请人： Steven K. Sullivan , Terrance R. Beale , Kristie Veith
发明人： Steven K. Sullivan , Terrance R. Beale , Kristie Veith
IPC分类号： G01R13/20
CPC分类号： G01R13/0254
摘要： A “no dead time” data acquisition system for a measurement instrument receives a digitized signal representing an electrical signal being monitored and generates from the digitized signal a trigger signal using a fast digital trigger circuit, the trigger signal including all trigger events within the digitized signal. The digitized signal is compressed as desired and delayed by a first-in, first-out (FIFO) buffer for a period of time to assure a predetermined amount of data prior to a first trigger event in the trigger signal. The delayed digitized signal is delivered to a fast rasterizer or drawing engine upon the occurrence of the first trigger event to generate a waveform image. The waveform image is then provided to a display buffer for combination with prior waveforms and/or other graphic inputs from other drawing engines. The contents of the display buffer are provided to a display at a display update rate to show a composite of all waveform images representing the electrical signal.
摘要翻译：用于测量仪器的“无死区时间”数据采集系统接收表示正在监视的电信号的数字化信号，并且使用快速数字触发电路从数字化信号产生触发信号，触发信号包括数字化信号内的所有触发事件。数字化信号根据需要被压缩并且由先入先出（FIFO）缓冲器延迟一段时间，以确保在触发信号中的第一触发事件之前的预定量的数据。延迟数字化信号在发生第一触发事件时被传送到快速光栅化器或绘图引擎以产生波形图像。然后将波形图像提供给显示缓冲器，以与来自其它绘图引擎的先前波形和/或其他图形输入组合。以显示更新率将显示缓冲器的内容提供给显示器，以显示表示电信号的所有波形图像的合成。

5. 发明授权

US07558936B2 Data management in long record length memory 失效
标题翻译：长记录长度内存中的数据管理
公开(公告)号：US07558936B2
公开(公告)日：2009-07-07
申请号：US11388926
申请日：2006-03-24
申请人： Terrance R. Beale , Steven K. Sullivan , Kristie L. Veith
发明人： Terrance R. Beale , Steven K. Sullivan , Kristie L. Veith
IPC分类号： G06F12/00
CPC分类号： G06F5/14 , G01R13/029
摘要： A data management method for a long record length memory that is used for data acquisition writes data samples into an initial circular buffer within the memory having a size equal to a pre-trigger time. When a first trigger event occurs, the data samples are then written into a linear region after the circular buffer within the memory. The data sample acquisition in the linear region continues until a post-trigger and new pre-trigger time have elapsed after a last trigger event, at which point the acquisition terminates and the new pre-trigger time becomes a new circular buffer for a next trigger event. In this way all trigger events are captured with associated pre-trigger and post-trigger data.
摘要翻译：用于数据采集的长记录长度存储器的数据管理方法将数据样本写入具有等于预触发时间的大小的存储器内的初始循环缓冲器。当发生第一触发事件时，数据样本然后被写入存储器中的循环缓冲器之后的线性区域。线性区域中的数据样本采集继续，直到最后一次触发事件发生后触发和新的预触发时间，此时采集终止，新的预触发时间成为新的循环缓冲区，用于下一个触发事件。以这种方式，所有触发事件都将被捕获与相关的预触发和后触发数据。

6. 发明申请

US20090063072A1 LOGIC ANALYZER USING A DIGITAL FILTER 失效
标题翻译：使用数字滤波器的逻辑分析仪
公开(公告)号：US20090063072A1
公开(公告)日：2009-03-05
申请号：US11850122
申请日：2007-09-05
申请人： Steven K. SULLIVAN , Michael S. HAGEN
发明人： Steven K. SULLIVAN , Michael S. HAGEN
IPC分类号： G06F11/25 , G01R31/3177
CPC分类号： G01R31/3177
摘要： A logic analyzer having clock channels and data channels includes digitizer followed by a digital filter in each channel, the digital filter compensating for losses in signal fidelity in a signal under test. The resulting enhanced multi-bit samples are stored in respective waveform memories for subsequent display as analog waveforms and as logic data. The multi-bit samples from each channel are re-sampled by a regenerated sample clock to determine the logic values of the signal at precise times. For high speed serial data, each channel is divided into multiple clock channels and sampling channels, the outputs from the clock channels being phase adjusted to provide a precise sample clock to the sampling channels and the outputs from the sampling channels being combined to form a serial data output.
摘要翻译：具有时钟通道和数据通道的逻辑分析器包括数字转换器，随后是每个通道中的数字滤波器，数字滤波器补偿被测信号中信号保真度的损失。所得到的增强的多位采样被存储在相应的波形存储器中，用于随后显示为模拟波形和逻辑数据。来自每个通道的多位采样由再生的采样时钟重新采样，以在精确时间确定信号的逻辑值。对于高速串行数据，每个通道分为多个时钟通道和采样通道，来自时钟通道的输出被相位调整，以向采样通道提供精确的采样时钟，并且来自采样通道的输出被组合以形成串行数据输出。

7. 发明申请

US20080042666A1 Multiple probe acquisition system 有权
标题翻译：多探头采集系统
公开(公告)号：US20080042666A1
公开(公告)日：2008-02-21
申请号：US11505566
申请日：2006-08-16
申请人： Steven K. Sullivan
发明人： Steven K. Sullivan
IPC分类号： G01R31/02
CPC分类号： G01R1/06766 , G01R13/02 , G01R31/31725 , G01R31/31726 , G01R31/3177
摘要： A multiple probe acquisition system, such as for use with a value instrument, uses probes where each probe includes an acquisition circuit for acquiring from a circuit under test an electrical signal as digital data at a high rate, and then transferring the digital data from the probe to the instrument at a lower rate over a data bus for processing and display. The probe may be used to acquire analog waveforms or logic data from the electrical signal. The probe provides a very low input capacitance to the circuit under test, minimizing signal distortion, and is relatively inexpensive. The probes are time aligned by detecting when one of the probes generates a trigger, and timing the other probes to stop acquisition simultaneously so the data is synchronized among the probes.
摘要翻译：诸如与价值仪器一起使用的多探头采集系统使用探针，其中每个探针包括采集电路，用于以高速率将电信号作为数字数据从被测电路获取，然后将数字数据从通过数据总线以较低的速率探测仪器进行处理和显示。探头可用于从电信号中采集模拟波形或逻辑数据。该探头为被测电路提供了非常低的输入电容，使信号失真最小化，并且相对便宜。通过检测何时其中一个探针产生触发，并且定时其他探测器同时停止采集，探针是时间对齐的，以便数据在探头之间同步。

8. 发明授权

US07284025B2 DDS pulse generator architecture 有权
标题翻译： DDS脉冲发生器架构
公开(公告)号：US07284025B2
公开(公告)日：2007-10-16
申请号：US10739591
申请日：2003-12-18
申请人： Steven K. Sullivan , Raymond L. Veith , Iwao Akiyama , Yasumasa Fujisawa
发明人： Steven K. Sullivan , Raymond L. Veith , Iwao Akiyama , Yasumasa Fujisawa
IPC分类号： G06F1/02
CPC分类号： G06F1/0328
摘要： A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.
摘要翻译： DDS脉冲发生器具有累加相位增量值以产生相位累加器值的累加器，并且具有包含脉冲波形的数字表示的查找表，使得响应于相位从查找表产生脉冲输出信号累加器值。为了改变脉冲输出信号的周期而不改变边沿位置，使用可编程的模数值。地址映射器位于查找表的累加器和地址线之间，以将相位累加器值的上升沿和下降沿部分映射到查找表的大区域，而对应于高逻辑电平和低逻辑电平的相位累加器值映射到查找表的小区域。所产生的脉冲输出信号容易独立地控制周期和脉冲宽度以及上升和下降沿速度。通过更好地利用查找表，可以产生具有低重复率或脉冲的非常窄的脉冲，其中上升时间和下降时间与周期非常不同。

9. 发明授权

US07038896B2 Solid state motor protector 有权
标题翻译：固态电机保护器
公开(公告)号：US07038896B2
公开(公告)日：2006-05-02
申请号：US10318960
申请日：2002-12-13
申请人： Steven K. Sullivan , Kevin R. French
发明人： Steven K. Sullivan , Kevin R. French
IPC分类号： H02H5/04
CPC分类号： H01H61/002
摘要： A solid state motor protector has a first PTC chip (positive temperature coefficient of resistivity) electrically connected in series relation with a second resistor having a generally fixed temperature coefficient of resistivity and mechanically coupled to the first resistor in close/direct thermal coupling. Another embodiment has a plate like isolator (52) formed with an opening receiving a polymer PTC chip (58) and having terminals (54, 56) which serve as fixed resistors. Yet another embodiment has an additional PTC resistor and a fixed resistor used in a motor reversing mechanism. Still another embodiment has a fixed resistor on either side of a PTC resistor for use in protecting the windings of a single phase motor. Another embodiment has a stack of polymer PTC resistor chips (82a–82d) with one chip serving as a voltage blocking chip and the other chip serving as fixed resistors.
摘要翻译：固态电动机保护器具有与具有大致固定的电阻率温度系数的第二电阻器串联连接的第一PTC芯片（正电温度系数），并以紧密/直接的热耦合机械耦合到第一电阻器。另一实施例具有板状隔离器（52），其形成有接收聚合物PTC芯片（58）并具有用作固定电阻器的端子（54,56）的开口。另一个实施例具有用于电机反转机构中的附加PTC电阻器和固定电阻器。另一个实施例在用于保护单相电动机的绕组的PTC电阻器的两侧上具有固定电阻器。另一个实施例具有一堆聚合物PTC电阻芯片（82a-82d），其中一个芯片用作电压阻挡芯片，另一个芯片用作固定电阻器。

10. 发明授权

US4712058A Active load network 失效
标题翻译：主动负载网络
公开(公告)号：US4712058A
公开(公告)日：1987-12-08
申请号：US888908
申请日：1986-07-22
申请人： Christopher W. Branson , Steven K. Sullivan
发明人： Christopher W. Branson , Steven K. Sullivan
IPC分类号： G01R31/26 , G01R19/165 , G01R31/30 , G01R31/319 , G01R19/00
CPC分类号： G01R31/31924 , G01R19/16557
摘要： An active load network for a device under test includes a logic circuit for anticipating the output state of the device under test and for turning on either a current source of a current sink to properly load its output. The current sink and current source each comprise a pair of CMOS transistors connected in series. One of each transistor pair turns on to either source or sink current and the other provides a variable impedance controlled by the voltage at its gate to regulate the amount of current. A pull-to-center transmission gate is also provided which pulls the output of the device under test to a level between a logic high and logic low when it is turned off.
摘要翻译：用于待测器件的有源负载网络包括用于预测被测器件的输出状态的逻辑电路，以及用于接通电流源的电流源以正确加载其输出。电流源和电流源各自包括串联连接的一对CMOS晶体管。每个晶体管对中的一个导通到源极或吸收电流，另一个提供由其栅极处的电压控制的可变阻抗，以调节电流量。还提供了一种拉到中心的传输门，当被关闭时，将被测器件的输出拉到逻辑高电平和逻辑低电平之间的电平。

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