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1. 发明申请

US20100219481A1 METHOD FOR MANUFACTURING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF 审中-公开
标题翻译：制造双功能半导体器件的半导体器件及其半导体器件的制造方法
公开(公告)号：US20100219481A1
公开(公告)日：2010-09-02
申请号：US12684803
申请日：2010-01-08
申请人： Joshua Tseng , Yasutoshi Okuno , Lars-Ake Ragnarsson , Tom Schram , Stefan Kubicek , Thomas Y. Hoffmann , Naohisa Sengoku
发明人： Joshua Tseng , Yasutoshi Okuno , Lars-Ake Ragnarsson , Tom Schram , Stefan Kubicek , Thomas Y. Hoffmann , Naohisa Sengoku
IPC分类号： H01L27/092 , H01L21/28
摘要： A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack.
摘要翻译：公开了一种用于制造双功能功能装置的方法。在一个方面，该方法包括在基底中的第一和第二区域。该方法包括在具有第一功能的第一区域中形成第一晶体管。随后，在具有不同功函数的第二区域中形成第二晶体管。形成第一晶体管的过程包括提供在第一栅极介电层上具有第一栅极介电层和第一栅极介电覆盖层的第一栅极电介质堆叠，执行热处理以修改第一栅极电介质堆叠，修改的第一栅极限定第一功函数的电介质叠层，在修改的第一栅极电介质堆叠上提供第一金属栅极电极层，以及对第一金属栅极电极层和修改的第一栅极电介质堆叠进行构图。

2. 发明申请

US20100032733A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100032733A1
公开(公告)日：2010-02-11
申请号：US12580573
申请日：2009-10-16
申请人： Satoru ITOU , Yasutoshi Okuno , Takashi Nakabayashi
发明人： Satoru ITOU , Yasutoshi Okuno , Takashi Nakabayashi
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device includes: a semiconductor substrate having an element formation region containing impurities of a first conductivity type; a gate electrode formed on the element formation region with a gate insulating film interposed therebetween; and a silicon alloy layer formed on a lateral side of the gate electrode in the element formation region, and containing impurities of a second conductivity type. A boundary layer containing impurities of the second conductivity type is formed between the silicon alloy layer and the element formation region.
摘要翻译：半导体器件包括：具有包含第一导电类型的杂质的元素形成区域的半导体衬底; 形成在元件形成区域上的栅电极，其间插入有栅极绝缘膜; 以及形成在元件形成区域中的栅电极的侧面上并且包含第二导电类型的杂质的硅合金层。在硅合金层和元件形成区之间形成含有第二导电型杂质的边界层。

3. 发明授权

US07446015B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07446015B2
公开(公告)日：2008-11-04
申请号：US11006665
申请日：2004-12-08
申请人： Yasutoshi Okuno , Masaru Yamada
发明人： Yasutoshi Okuno , Masaru Yamada
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , H01L21/76229 , H01L27/0207
摘要： A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of the isolation regions on the operation characteristics of elements formed in the element formation regions and a plurality of dummy features are formed in the stress effect relief region and other part of the circuit formation region than the element formation regions at predetermined distances, the dummy features having the same composition as the element formation regions and predetermined planar dimensions. The predetermined planar dimensions of the dummy features are defined by longitudinal and transverse dimensions most frequently found in the plurality of element formation regions formed in the circuit formation region or selected dimensions of the element formation regions. The predetermined distances between the dummy features are specified as the minimum allowable value in respect of the manufacture of the elements.
摘要翻译：半导体器件包括电路形成区域，其形成在半导体衬底中并且包括被隔离区包围的多个元件形成区域。在电路形成区域的周围形成预定宽度的应力作用缓和区域，以减轻隔离区域对形成在元件形成区域中的元件的操作特性的应力作用，并且在应力效应释放中形成多个虚拟特征区域和电路形成区域的其他部分比元件形成区域预定距离，虚拟特征具有与元件形成区域相同的组成和预定的平面尺寸。虚拟特征的预定平面尺寸由在电路形成区域中形成的多个元件形成区域或元件形成区域的选定尺寸中最常见的纵向和横向尺寸限定。虚拟特征之间的预定距离被指定为关于元件的制造的最小允许值。

4. 发明授权

US07253436B2 Resistance defect assessment device, resistance defect assessment method, and method for manufacturing resistance defect assessment device 有权
标题翻译：电阻缺陷评估装置，电阻缺陷评估方法和制造电阻缺陷评估装置的方法
公开(公告)号：US07253436B2
公开(公告)日：2007-08-07
申请号：US10895833
申请日：2004-07-22
申请人： Michikazu Matsumoto , Yasutoshi Okuno , Katsuyoshi Joukyu , Tetsuya Matsutani
发明人： Michikazu Matsumoto , Yasutoshi Okuno , Katsuyoshi Joukyu , Tetsuya Matsutani
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , G01R31/2853
摘要： A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.
摘要翻译：一种电阻缺陷评估装置，设置在用于评估集成电路器件的部件中的电阻变化缺陷的晶片上，所述电阻缺陷评估装置包括能够测量每个芯片区域中的电阻变化分量的电阻变化分量作为电阻变化缺陷的测试图案，晶片的每个照射区域，其中设置包括在一个芯片区域或一个照射区域中的测试图案的数量，使得可以估计集成电路器件的产量。

5. 发明授权

US07249343B2 In-plane distribution data compression method, in-plane distribution measurement method, in-plane distribution optimization method, process apparatus control method, and process control method 有权
标题翻译：平面内分布数据压缩方法，平面内分布测量方法，面内分布优化方法，过程装置控制方法和过程控制方法
公开(公告)号：US07249343B2
公开(公告)日：2007-07-24
申请号：US10891112
申请日：2004-07-15
申请人： Yasutoshi Okuno
发明人： Yasutoshi Okuno
IPC分类号： G06F17/50 , G06F19/00 , G06K9/00
CPC分类号： H01L22/20
摘要： After a process is performed on a substrate, the in-plane distribution over the substrate is measured. Measured data of the in-plane distribution which is obtained by the measurement is stored. A model formula of the in-plane distribution is calculated from the stored measured data. The measured data is compared with the model formula. A set of parameters of the model formula is calculated, and the calculated parameters are stored as data of the in-plane distribution over the substrate. The measured data includes measurement coordinates over the substrate. The model formula is obtained by modeling the tendency that the in-plane distribution concentrically varies and the tendency that the in-plane distribution varies along a diameter direction.
摘要翻译：在基板上进行处理之后，测量衬底上的面内分布。存储通过测量获得的平面内分布的测量数据。根据存储的测量数据计算面内分布的模型公式。将测量数据与模型公式进行比较。计算出模型公式的一组参数，将计算出的参数作为平面分布的数据存储在基板上。测量数据包括基板上的测量坐标。模型公式通过模拟面内分布同心变化的趋势和面内分布沿直径方向变化的趋势来获得。

6. 发明申请

US20060189087A1 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US20060189087A1
公开(公告)日：2006-08-24
申请号：US11356959
申请日：2006-02-21
申请人： Yasutoshi Okuno , Michikazu Matsumoto
发明人： Yasutoshi Okuno , Michikazu Matsumoto
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.

7. 发明授权

US06265262B1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06265262B1
公开(公告)日：2001-07-24
申请号：US09587363
申请日：2000-06-02
申请人： Yasutoshi Okuno , Akihiko Tsuzumitani , Yoshihiro Mori
发明人： Yasutoshi Okuno , Akihiko Tsuzumitani , Yoshihiro Mori
IPC分类号： H01L218242
CPC分类号： H01L21/7687 , H01L21/28518 , H01L21/76849 , H01L21/76889 , H01L27/10852 , H01L28/60
摘要： A silicon film is formed within a contact hole formed in a first insulating film on a semiconductor substrate in a manner that an upper portion of the contact hole remains, and a cobalt film is then deposited on the silicon film. Thereafter, a heat treatment is carried out so as to react the silicon film with the cobalt film, thereby forming a cobalt silicide layer in the surface portion of the silicon film. A barrier layer is formed on the cobalt silicide layer so as to completely fill the contact hole, and thus, a plug including the polysilicon film, the cobalt silicide layer and the barrier layer is formed. After a recess is formed in a second insulating film deposited on the first insulating film so as to expose the top surface of the plug, a capacitor bottom electrode, a capacitor dielectric film and a capacitor top electrode are successively formed in the recess.
摘要翻译：在半导体基板上形成在第一绝缘膜上的接触孔内形成硅膜，使得保留接触孔的上部，然后在硅膜上沉积钴膜。此后，进行热处理以使硅膜与钴膜反应，从而在硅膜的表面部分形成钴硅化物层。在硅化钴层上形成阻挡层，以完全填充接触孔，从而形成包括多晶硅膜，硅化钴层和阻挡层的插塞。在沉积在第一绝缘膜上的第二绝缘膜中形成凹部以暴露插头的顶面之后，在凹部中依次形成电容器底部电极，电容器电介质膜和电容器顶部电极。

8. 发明授权

US06251749B1 Shallow trench isolation formation with sidewall spacer 有权
公开(公告)号：US06251749B1
公开(公告)日：2001-06-26
申请号：US09394785
申请日：1999-09-13
申请人： Shigeru Kuroda , Yasutoshi Okuno , Ken Numata
发明人： Shigeru Kuroda , Yasutoshi Okuno , Ken Numata
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.

9. 发明授权

US08872284B2 FinFET with metal gate stressor 有权
标题翻译： FinFET与金属栅应力
公开(公告)号：US08872284B2
公开(公告)日：2014-10-28
申请号：US13425218
申请日：2012-03-20
申请人： Andrew Joseph Kelly , Yasutoshi Okuno , Pei-Shan Chien , Wei-Hsiung Tseng
发明人： Andrew Joseph Kelly , Yasutoshi Okuno , Pei-Shan Chien , Wei-Hsiung Tseng
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L21/28556 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L29/0653 , H01L29/7845 , H01L29/785
摘要： A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.
摘要翻译：提供了一种用于鳍式场效应晶体管（FinFET）器件的栅极应力器。闸应力器包括地板，第一应力侧壁和第二应力侧壁。地板形成在栅极层的第一部分上。栅极层设置在浅沟槽隔离（STI）区域的上方。第一应力侧壁形成在栅极层的第二部分上。栅极层的第二部分设置在散热片的侧壁上。第二应力侧壁形成在栅极层的第三部分上。栅极层的第三部分设置在与散热片间隔开的结构的侧壁上。第一应力侧壁和第二应力侧壁不超过翅片的高度。

10. 发明授权

US08759920B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08759920B2
公开(公告)日：2014-06-24
申请号：US13486343
申请日：2012-06-01
申请人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
发明人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
IPC分类号： H01L21/70
CPC分类号： H01L21/823814 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。常见的接触特征是自对准接触。

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