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1. 发明授权

US06448862B1 Single event upset immune oscillator circuit 有权
标题翻译：单次事件失调免疫振荡电路
公开(公告)号：US06448862B1
公开(公告)日：2002-09-10
申请号：US09667040
申请日：2000-09-21
申请人： Joseph Yoder , Nadim Haddad
发明人： Joseph Yoder , Nadim Haddad
IPC分类号： H03K3354
CPC分类号： H03K3/354 , H03K3/013 , H03K3/03
摘要： A single event effect immune oscillator circuit is disclosed. The single event upset immune oscillator circuit includes an odd number of logic circuit blocks connecting in series to provide a continuous pulse signal at an output of the oscillator circuit. Each logic circuit block has a first input, a second input, and an output. For a series of logic circuit blocks i, where i=1 to n (n is an odd number), the output of a logic circuit block i is connected to a first input of a logic circuit block i+1. The output of the logic circuit block i is also connected to a first input of a logic circuit block i+x, wherein x is an odd number greater than one and less than or equal to n.
摘要翻译：公开了一种单一的事件效应免疫振荡器电路。单次事件失调免疫振荡器电路包括串联连接的奇数个逻辑电路块，以在振荡器电路的输出端提供连续的脉冲信号。每个逻辑电路块具有第一输入，第二输入和输出。对于一系列逻辑电路块i，其中i = 1至n（n为奇数），逻辑电路块i的输出连接到逻辑电路块i + 1的第一输入。逻辑电路块i的输出也连接到逻辑电路块i + x的第一输入，其中x是大于1且小于或等于n的奇数。

2. 发明授权

US06392474B1 Circuit for filtering single event effect (see) induced glitches 有权
标题翻译：用于过滤单个事件效应的电路（见）引起的毛刺
公开(公告)号：US06392474B1
公开(公告)日：2002-05-21
申请号：US09651156
申请日：2000-08-30
申请人： Bin Li , Dave C. Lawson , Joseph Yoder
发明人： Bin Li , Dave C. Lawson , Joseph Yoder
IPC分类号： H03K500
CPC分类号： H03K5/1252
摘要： A circuit for filtering single event effect (SEE) induced glitches is disclosed. The circuit for filtering SEE induced glitches comprises an SEE immune latch circuit and a delay element. The SEE immune latch circuit includes a first input, a second input, and an output. The SEE immune latch changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. The first input of the SEE immune latch circuit is directly connected to a signal input, and the second input of the SEE immune latch circuit is connected to the signal input via the delay element. The delay element provides a signal delay time equal to or greater than a pulse width of an SEE induced glitch but less than a pre-determined pulse width of an incoming signal at the signal input under normal operation. By connecting the delay element between the signal input and the second input of the SEE immune latch circuit, a temporal separation greater that the duration of an SEE induced glitch can be achieved on the data being drive into the first and the second inputs of the SEE immune latch circuit. As a result, SEE induced glitches will not be written into the SEE immune latch circuit.
摘要翻译：公开了一种用于滤除单事件效应（SEE）引起的毛刺的电路。 SEE诱导毛刺滤波电路包括SEE免疫锁存电路和延迟元件。 SEE免疫锁定电路包括第一输入端，第二输入端和输出端。只有当具有相同极性的输入输入信号同时在第一输入端和第二输入端同时施加时，SEE免疫锁定器从一个状态改变到另一个状态。 SEE免疫锁定电路的第一个输入直接连接到信号输入，SEE免疫锁存电路的第二个输入端通过延迟元件连接到信号输入端。延迟元件提供等于或大于SEE诱发毛刺的脉冲宽度但小于在正常操作下的信号输入处的输入信号的预定脉冲宽度的信号延迟时间。通过连接SEE免疫锁存电路的信号输入和第二输入之间的延迟元件，可以在驱动到SEE的第一和第二输入端的数据上实现SEE引起的毛刺持续时间的时间间隔免疫锁定电路。因此，SEE诱发的毛刺不会写入SEE免疫锁定电路。

3. 发明授权

US07013441B2 Method for modeling integrated circuit yield 失效
标题翻译：集成电路产量建模方法
公开(公告)号：US07013441B2
公开(公告)日：2006-03-14
申请号：US10605379
申请日：2003-09-26
申请人： Jeanne P. Bickford , Edward K. Evans , Sean Horner , Raymond J. Rosner , Andrew Wienick , Joseph Yoder
发明人： Jeanne P. Bickford , Edward K. Evans , Sean Horner , Raymond J. Rosner , Andrew Wienick , Joseph Yoder
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in the design database; (b) selecting library elements from the design database to include in a proposed design for the integrated circuit; (c) generating an equivalent circuit count of the proposed design based on the normalization factors and a count of each different library element included in the proposed design; and (d) calculating a predicted manufacturing yield based on the equivalent circuit count, a predicted density of manufacturing defects and an area of the proposed integrated circuit chip.
摘要翻译：一种用于预测所提出的集成电路的制造产量的方法和系统。该方法包括：按照所述的顺序：（a）在设计数据库中提供多个不同的集成电路库元件，每个库元件链接到相应的归一化因子设计数据库; （b）从设计数据库中选择库元素以包含在集成电路的拟议设计中; （c）基于归一化因子和所提出的设计中包括的每个不同的库元素的计数产生所提出的设计的等效电路数; 以及（d）基于等效电路数，制造缺陷的预测密度和所提出的集成电路芯片的面积来计算预计制造产量。

4. 发明申请

US20050071788A1 METHOD FOR MODELING INTEGRATED CIRCUIT YIELD 失效
标题翻译：用于建模集成电路的方法
公开(公告)号：US20050071788A1
公开(公告)日：2005-03-31
申请号：US10605379
申请日：2003-09-26
申请人： Jeanne Bickford , Edward Evans , Sean Horner , Raymond Rosner , Andrew Wienick , Joseph Yoder
发明人： Jeanne Bickford , Edward Evans , Sean Horner , Raymond Rosner , Andrew Wienick , Joseph Yoder
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in the design database; (b) selecting library elements from the design database to include in a proposed design for the integrated circuit; (c) generating an equivalent circuit count of the proposed design based on the normalization factors and a count of each different library element included in the proposed design; and (d) calculating a predicted manufacturing yield based on the equivalent circuit count, a predicted density of manufacturing defects and an area of the proposed integrated circuit chip.
摘要翻译：一种用于预测所提出的集成电路的制造产量的方法和系统。该方法包括：按照所述的顺序：（a）在设计数据库中提供多个不同的集成电路库元件，每个库元件链接到相应的归一化因子设计数据库; （b）从设计数据库中选择库元素以包含在集成电路的拟议设计中; （c）基于归一化因子和所提出的设计中包括的每个不同的库元素的计数产生所提出的设计的等效电路数; 以及（d）基于等效电路数，制造缺陷的预测密度和所提出的集成电路芯片的面积来计算预计制造产量。

5. 发明授权

US06779329B2 Vinous crop harvesting apparatus and method 失效
标题翻译：高产作物收获机及方法
公开(公告)号：US06779329B2
公开(公告)日：2004-08-24
申请号：US09960615
申请日：2001-09-21
申请人： Joseph Yoder , Matthew Moyer
发明人： Joseph Yoder , Matthew Moyer
IPC分类号： A01D4600
CPC分类号： A01D46/00 , A01D45/00
摘要： Harvesting methods and apparatus provide endless movable arrays of finger members for contacting and strippingly lifting fruits from plants in growing fields with each of the arrays being generally upstanding, longitudinally elongated and having at least a portion which is substantially planar along which the finger members endlessly move upwardly while strippingly lifting the fruits from the plants as the apparatus travels through the growing field.
摘要翻译：收获方法和装置提供无限可移动的指状构件阵列，用于接触和剥离生长田中植物的果实，其中每个阵列通常是直立的，纵向细长的并且具有至少一部分，其中手指构件沿着该部分不断地移动向上，当设备穿过生长区域时，从植物中剥离果实。

6. 发明授权

US06282877B1 Fruit and vegetable harvesting apparatus and methods 失效
标题翻译：水果和蔬菜收获设备和方法
公开(公告)号：US06282877B1
公开(公告)日：2001-09-04
申请号：US08672635
申请日：1996-06-28
申请人： Joseph Yoder
发明人： Joseph Yoder
IPC分类号： A01D4500
CPC分类号： A01D45/008 , A01D45/00 , A01D45/006
摘要： Method and apparatus for harvesting vinous crops includes cutting a fruit-carrying vine mass from its growing roots, sweeping the vine mass with rotary reel motion onto a upwardly inclined endless conveyor for carriage to a position of commencement of a first arcuate path and thereafter carrying the vine mass along the arcuate path by first lifting and then lowering the vine mass while imparting vibratory motion to the vine mass to separate fruit from vines of the mass.
摘要翻译：用于收获葡萄种植作物的方法和装置包括从其生根的根部切割携带果实的葡萄群，将具有旋转卷轴运动的藤质块旋转到向上倾斜的环形输送机上，以运送到第一弧形路径的开始位置，然后携带沿着弧形路径的葡萄树块通过首先提升然后降低葡萄藤质量，同时给藤蔓施加振动运动以将果实与群体的葡萄分离。

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