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1. 发明申请

US20110305651A1 SUNLESS TANNING COMPOSITIONS WITH NUCLEOPHILE FUNCTIONALIZED SULFONIC ACIDS 审中-公开
标题翻译：无核苷酸组成与核酸功能化硫酸
公开(公告)号：US20110305651A1
公开(公告)日：2011-12-15
申请号：US13155451
申请日：2011-06-08
申请人： Joseph Oreste Carnali , Wei-min Peng , Qiang Qiu , Zhijian Yang , Xiaoxia Yang
发明人： Joseph Oreste Carnali , Wei-min Peng , Qiang Qiu , Zhijian Yang , Xiaoxia Yang
IPC分类号： A61K8/46 , A61Q17/04
CPC分类号： A61K8/466 , A61Q19/04
摘要： Sunless tanning compositions with nucleophile functionalized sulfonic acids are described. The compositions are stable and result in excellent tanning results when sunless tanning agents like 1,3-dihydroxy-2-propanone are used.
摘要翻译：描述了具有亲核官能化磺酸的无鞣制组合物。当使用无阳光鞣剂如1,3-二羟基-2-丙酮时，组合物是稳定的并且产生优异的鞣制结果。

2. 发明授权

US08853693B2 Test structure for determination of TSV depth 有权
标题翻译：用于测定TSV深度的测试结构
公开(公告)号：US08853693B2
公开(公告)日：2014-10-07
申请号：US13423823
申请日：2012-03-19
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/00 , H01L21/768 , H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

3. 发明授权

US08338313B2 Method for nondestructive lift-off of GaN from sapphire substrate utilizing a solid-state laser 有权
标题翻译：使用固态激光器从蓝宝石衬底中非破坏性剥离GaN的方法
公开(公告)号：US08338313B2
公开(公告)日：2012-12-25
申请号：US12865728
申请日：2009-04-21
申请人： Guoyi Zhang , Yongjian Sun , Xiangning Kang , Zhizhong Chen , Zhijian Yang , Xinrong Yang
发明人： Guoyi Zhang , Yongjian Sun , Xiangning Kang , Zhizhong Chen , Zhijian Yang , Xinrong Yang
IPC分类号： H01L21/31
CPC分类号： H01L33/0079 , B23K26/40 , B23K2103/50 , C30B25/18 , C30B29/406 , C30B33/06
摘要： A method for nondestructive laser lift-off of GaN from sapphire substrates is disclosed. A solid-state laser is used as the laser source. A small laser-spot having a perimeter length of 3 to 1000 micrometers and a distance of two farthest corners or a longest diameter of no more than 400 micrometers is used for laser scanning point-by-point and line-by-line. The energy at the center of the laser-spot is the strongest and is gradually reduced toward the periphery. A nondestructive laser lift-off with a small laser-spot is achieved. The scanning mode of the laser lift-off is improved. Device lift-off can be achieved without the need of aiming. As a result, the laser lift-off process is simplified, and the efficiency is improved while the rejection rate is reduced. The obstacles of the industrialization of the laser lift-off process are removed.
摘要翻译：公开了一种用于蓝宝石衬底的GaN非破坏性激光剥离的方法。固体激光器用作激光源。使用周边长度为3〜1000微米，距离最远的两个角或最大直径不大于400微米的小型激光点，用于逐点和逐行的激光扫描。激光中心的能量最强，逐渐减少到周边。实现了具有小型激光点的非破坏性激光剥离。激光剥离的扫描模式得到改善。可以实现设备剥离，无需瞄准。结果，简化了激光剥离工艺，并且在抑制率降低的同时提高了效率。消除了激光剥离工艺的工业化障碍。

4. 发明授权

US08159814B2 Method of operating transistors and structures thereof for improved reliability and lifetime 有权
标题翻译：操作晶体管及其结构的方法，以提高可靠性和寿命
公开(公告)号：US08159814B2
公开(公告)日：2012-04-17
申请号：US12355815
申请日：2009-01-19
申请人： Ping-Chuan Wang , Zhijian Yang , Fernando J. Guarin , J. Edwin Hostetter , Kai D Feng
发明人： Ping-Chuan Wang , Zhijian Yang , Fernando J. Guarin , J. Edwin Hostetter , Kai D Feng
IPC分类号： H01G7/02 , G01R31/04
CPC分类号： H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.
摘要翻译：本发明的实施例提供一种半导体器件，其包括具有第一，第二和第三节点的晶体管器件; 以及具有至少一根导线的互连结构，并且所述导线具有第一和第二端，所述导线的第一端连接到晶体管器件的第一，第二和第三节点之一。导线是导电的并且适于在正常操作模式期间在第一方向上提供工作电流，并且适于在半导体器件的修复模式期间在与第一方向相反的第二方向上提供修复电流。在一个实施例中，晶体管器件是双极晶体管，其中第一，第二和第三节点是双极晶体管的发射极，基极和集电极。导线连接到发射极和集电极之一。还公开了用于半导体器件的半导体器件和电流供应电路的操作方法。

5. 发明授权

US07961032B1 Method of and structure for recovering gain in a bipolar transistor 有权
标题翻译：双极晶体管中恢复增益的方法和结构
公开(公告)号：US07961032B1
公开(公告)日：2011-06-14
申请号：US12627282
申请日：2009-11-30
申请人： Zhijian Yang , Ping-Chuan Wang , Kai Di Feng
发明人： Zhijian Yang , Ping-Chuan Wang , Kai Di Feng
IPC分类号： H03K17/60
CPC分类号： H03F1/302
摘要： A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain β of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ∝ (Δβ)2×exp [1/(Tam+Rth×le×VCER)], VCER=VBER+VCBR, and le=β×Ibr, β is the normal current gain of the transistor, Δβ is the target recovery gain of the transistor in percentage, Tam is the ambient temperature in degrees K, Ibr is the repair current to the base in μamps, Rth is the self-heating thermal resistance of the transistor in K/W, TR is in seconds. The invention further includes structures for implementing the method.
摘要翻译：一种在双极晶体管中恢复增益的方法，包括：提供一个包括发射极，集电极和设置在发射极和集电极之间的结之间的基极的双极晶体管; 使用工作电压和工作时间周期反向偏置设置在发射极和基极之间的结，使得电流增益＆bgr; 的晶体管劣化; 使晶体管怠速，并产生修复电流Ibr到基极，同时以第一修复电压（VEBR）向前偏置设置在发射极和基极之间的结，并且至少部分地同时反向偏置设置在集电极和具有第二修复电压（VCBR）的基座，用于修复时间段（TR），使得增益至少被回收; 其中VEBR，VCBR和TR具有比例关系：TRα（＆Dgr;＆bgr;）2×exp [1 /（Tam + Rth×le×VCER）]，VCER = VBER + VCBR，和le =＆bgr;×Ibr，＆bgr 是晶体管的正常电流增益，＆Dgr; 是晶体管的目标恢复增益百分比，谭是以K为单位的环境温度，Ibr是以μ为单位的基极修复电流，Rth是晶体管的自热热阻，K / W，TR在秒。本发明还包括用于实现该方法的结构。

6. 发明申请

US20110073858A1 Test Structure for Determination of TSV Depth 有权
标题翻译：测定TSV深度的测试结构
公开(公告)号：US20110073858A1
公开(公告)日：2011-03-31
申请号：US12566726
申请日：2009-09-25
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L23/48 , H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括第一TSV，电连接到第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

7. 发明申请

US20100331529A1 METHODS FOR INCREASING PROTEIN POLYETHYLENE GLYCOL (PEG) CONJUGATION 失效
标题翻译：增加蛋白质聚乙二醇（PEG）结合的方法
公开(公告)号：US20100331529A1
公开(公告)日：2010-12-30
申请号：US12875377
申请日：2010-09-03
申请人： Shukuan Li , Zhijian Yang , Xinghua Sun , Yuying Tan , Shigeo Yagi
发明人： Shukuan Li , Zhijian Yang , Xinghua Sun , Yuying Tan , Shigeo Yagi
IPC分类号： C07K1/107
CPC分类号： A61K47/48215 , A61K38/51 , A61K47/60 , C07K1/1077 , C12N9/88
摘要： The present invention relates to highly conjugated proteins and methods for making such proteins. In particular, the present invention relates to methods for linking additional sites to a protein for conjugation with activated polyethylene glycol (PEG) linkers, without denaturing the protein. The invention also relates to highly conjugated proteins with decreased immunogenicity and increased circulating half-life.
摘要翻译：本发明涉及高度缀合的蛋白质及其制备方法。特别地，本发明涉及将附加位点与蛋白质连接以与活化聚乙二醇（PEG）接头共轭的方法，而不使蛋白质变性。本发明还涉及具有降低的免疫原性和增加的循环半衰期的高度缀合的蛋白质。

8. 发明申请

US20100261318A1 3D CHIP-STACK WITH FUSE-TYPE THROUGH SILICON VIA 有权
公开(公告)号：US20100261318A1
公开(公告)日：2010-10-14
申请号：US12822459
申请日：2010-06-24
申请人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
发明人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/82
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5256 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/3011 , H01L2924/00014
摘要： Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

9. 发明申请

US20100260757A1 USE OF PLP WITH PEG-rMETase IN VIVO FOR ENHANCED EFFICACY 审中-公开
标题翻译：在血液中使用PEG-rMETase的PLP用于增强功效
公开(公告)号：US20100260757A1
公开(公告)日：2010-10-14
申请号：US12824116
申请日：2010-06-25
申请人： Shigeo YAGI , Zhijian Yang , Shukuan Li , Xinghua Sun , Yuying Tan
发明人： Shigeo YAGI , Zhijian Yang , Shukuan Li , Xinghua Sun , Yuying Tan
IPC分类号： A61K38/43 , A61K38/51 , A61K39/395
CPC分类号： A61K38/51 , A61K31/675 , A61K31/74 , A61K2300/00
摘要： This invention relates to methods of modifying pyridoxal 5′ phosphate (PLP) dependent enzymes to extend the serum half-life of the enzyme, extend the in vivo period of methionine depletion in a host, and decrease the immunogenicity of the enzyme. A preferred PLP-dependent enzyme to be modified is a methioninase, preferably a recombinant methioninase (rMETase). The invention further relates to compositions comprising a modified PLP-dependent enzyme and methods of using the same.
摘要翻译：本发明涉及修饰吡哆醛5'磷酸（PLP）依赖性酶的方法以延长酶的血清半衰期，延长宿主中甲硫氨酸消耗的体内周期，并降低酶的免疫原性。待修饰的优选的PLP依赖性酶是蛋氨酸酶，优选重组蛋氨酸酶（rMETase）。本发明还涉及包含修饰的PLP依赖性酶的组合物及其使用方法。

10. 发明申请

US20070205434A1 METHODOLOGY FOR RECOVERY OF HOT CARRIER INDUCED DEGRADATION IN BIPOLAR DEVICES 有权
标题翻译：在双极器件中恢复热载体诱导降解的方法
公开(公告)号：US20070205434A1
公开(公告)日：2007-09-06
申请号：US11744621
申请日：2007-05-04
申请人： Fernando Guarin , J. Hostetter , Stewart Rauch , Ping-Chuan Wang , Zhijian Yang
发明人： Fernando Guarin , J. Hostetter , Stewart Rauch , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L29/70 , H01L21/8222
CPC分类号： H01L29/7304 , H01L29/7378
摘要： A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal or a spike anneal.
摘要翻译：提供了一种用于回收由雪崩热载体引起的降解的方法，其包括使表现出雪崩降解的空闲双极晶体管经历热退火步骤，所述热退火步骤增加了晶体管的温度，从而恢复了双极晶体管的雪崩劣化。在一个实施例中，退火源是自发热结构，其是与双极晶体管的发射极并排放置的含Si电阻器。在恢复步骤期间，包括自发热结构的双极晶体管被置于空闲模式（即，没有偏压），并且来自单独电路的电流流过自热结构。在本发明的另一个实施例中，退火步骤是在双极晶体管的周围提供高正向电流（围绕峰值fT电流或更大）的结果，同时在低于雪崩条件（V CB）的情况下运行超过1 V）。在上述条件下，可以回收约40％以上的降解。在本发明的又一实施例中，热退火步骤可以包括快速热退火（RTA），炉退火，激光退火或尖峰退火。

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