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    • 5. 发明授权
    • Rendering shaded areas with boundary-localized pseudo-random noise
    • 渲染具有边界局部伪随机噪声的阴影区域
    • US5179641A
    • 1993-01-12
    • US370732
    • 1989-06-23
    • Todd CominsWillem Engelse
    • Todd CominsWillem Engelse
    • G06T11/00
    • G06T11/001G09G3/2044G09G3/2048G09G5/026G09G2320/0247G09G5/06
    • A computer graphics technique for rendering shaded areas by using pseudo-random noise localized to image boundaries is disclosed. Calculated pixel values are initially generated using an arithmetic accuracy larger than the word size of an associated bitmap memory. The calculated pixel values thus have a most significant portion, corresponding to the portion which is to be stored in bitmap memory, and a least significant portion, corresponding to the additional accuracy. Pseudo-random noise, preferably generated by a linear feedback shift register, is then added to some or all of the least significant portion, and the carry output from this operation is added to the most significant portion. The most significant portion is then written into bitmap memory. Changes in the value of the integer portion thus occur with increased frequency as the distance to an intensity boundary decreases, since the random noise causes the dithering to occur with increased frequency. The result is a more natural display than would otherwise be available with a given bitmap memory word size.
    • 公开了一种用于通过使用局限于图像边界的伪随机噪声来渲染阴影区域的计算机图形技术。 最初使用大于关联位图存储器的字大小的算术精度生成计算像素值。 因此,所计算的像素值具有对应于要存储在位图存储器中的部分和对应于附加精度的最低有效部分的最高有效部分。 然后,优选地由线性反馈移位寄存器生成的伪随机噪声被添加到最不重要部分的一些或全部,并且来自该操作的进位输出被添加到最高有效部分。 最重要的部分然后写入位图存储器。 随着距离强度边界的距离减小,整数部分的值的变化随着频率的增加而发生,因为随机噪声导致抖动以增加的频率发生。 结果是比给定的位图存储器字大小可能的更自然的显示。
    • 7. 发明申请
    • Cache coherency mechanism
    • 缓存一致机制
    • US20050228952A1
    • 2005-10-13
    • US10823300
    • 2004-04-13
    • David MayhewKarl MeierTodd Comins
    • David MayhewKarl MeierTodd Comins
    • G06F12/00G06F12/08
    • G06F12/0817
    • The present invention minimizes the amount of traffic that traverses the fabric in support of the cache coherency protocol. It also allows rapid transmission of all traffic associated with the cache coherency protocol, so as to minimize latency and maximize performance. A fabric is used to interconnect a number of processing units together. The switches are able to recognize incoming traffic related to the cache coherency protocol and then move these messages to the head of that switch's output queue to insure fast transmission. Also, the traffic related to the cache coherency protocol can interrupt an outgoing message, further reducing latency. The switch incorporates a memory element, dedicated to the cache coherency protocol, which tracks the contents of all of the caches of all of the processors connected to the fabric. In this way, the fabric can selectively transmit traffic only to the processors where it is relevant.
    • 本发明最大限度地减少了支持高速缓存一致性协议的通过结构的业务量。 它还允许与高速缓存一致性协议相关联的所有业务的快速传输,以便最小化等待时间并最大化性能。 织物用于将多个处理单元互连在一起。 交换机能够识别与缓存一致性协议相关的传入流量,然后将这些消息移动到该交换机的输出队列的头部以确保快速传输。 此外,与缓存一致性协议相关的流量可以中断外发消息,进一步减少延迟。 该交换机包含专用于高速缓存一致性协议的存储器元件,其跟踪连接到该结构的所有处理器的所有高速缓存的内容。 以这种方式,结构可以选择性地将流量传输到与其相关的处理器。