专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10424043B1 Efficiently enqueuing workloads from user mode to hardware across privilege domains 有权
公开(公告)号：US10424043B1
公开(公告)日：2019-09-24
申请号：US16025718
申请日：2018-07-02
申请人： Joseph Koston , Ankur Shah , Murali Ramadoss , Jeffery Boles , Balaji Vembu
发明人： Joseph Koston , Ankur Shah , Murali Ramadoss , Jeffery Boles , Balaji Vembu
IPC分类号： G06T1/20 , G06F21/74 , G06T15/00 , G06F9/50 , G06T1/60 , G09G5/36
摘要： Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing cores, a shared buffer accessible to a user mode driver (UMD) associated with an application in an unprivileged domain, the UMD to write one or more commands to the shared buffer, and a controller parse a workload in the shared buffer to identify one or more commands in the workload, the workload added by the application executing in the unprivileged domain, associate a trigger with a command in the workload, transfer the workload to one or more components of the graphics processing apparatus for execution, and upon execution of the command associated with the trigger, sample the shared buffer to identify a new workload added to the shared buffer. The one or more components of the graphics processing apparatus automatically execute the new workload added to the shared buffer.

2. 发明申请

US20140208047A1 METHOD AND DEVICE TO DISTRIBUTE CODE AND DATA STORES BETWEEN VOLATILE MEMORY AND NON-VOLATILE MEMORY 有权
标题翻译：在挥发性内存与非易失性存储器之间分配代码和数据存储的方法和设备
公开(公告)号：US20140208047A1
公开(公告)日：2014-07-24
申请号：US13977295
申请日：2011-12-28
申请人： Balaji Vembu , Murali Ramadoss
发明人： Balaji Vembu , Murali Ramadoss
IPC分类号： G06F3/06
CPC分类号： G06F3/0638 , G06F3/0604 , G06F3/0683 , G06F12/0292 , G06F2212/205 , G06T1/60 , G11C14/0045 , Y02D10/13
摘要： A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (PCMS) device, storing one or more static data segments of the software application in the PCMS device, and storing one or more volatile data segments of the software application in a volatile memory device. The method then allocates an address mapping table with at least a first address pointer to point to each of the one or more static code segments, at least a second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.
摘要翻译：描述了在易失性和非易失性存储器之间分发代码和数据存储的方法，设备和系统。在一个实施例中，该方法包括将具有交换机（PCMS）设备的软件应用的一个或多个静态代码段存储在相变存储器中，将该软件应用的一个或多个静态数据段存储在PCMS设备中，并存储一个或多个在易失性存储器件中软件应用的更易变的数据段。该方法然后将至少一个第一地址指针的地址映射表分配给一个或多个静态代码段中的每一个，至少第二地址指针指向一个或多个静态数据段中的每一个，并且至少指向一个或多个易失性数据段中的每一个的第三地址指针。

3. 发明申请

US20160189681A1 Ordering Mechanism for Offload Graphics Scheduling 有权
标题翻译：卸载图形调度的排序机制
公开(公告)号：US20160189681A1
公开(公告)日：2016-06-30
申请号：US14582972
申请日：2014-12-24
申请人： Bryan R. White , Balaji Vembu , Murali Ramadoss , Altug Koker , Aditya Navale
发明人： Bryan R. White , Balaji Vembu , Murali Ramadoss , Altug Koker , Aditya Navale
IPC分类号： G09G5/18 , G06T1/60 , G06T1/20
CPC分类号： G09G5/18 , G06T1/20 , G09G5/026 , G09G5/14 , G09G5/363 , G09G2320/106 , G09G2340/02 , G09G2360/121 , G09G2360/18 , G09G2370/16
摘要： Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.
摘要翻译：这里描述的是与在“处理器到处理器”切换或事务中的命令和图形上下文从相干到非相干存储器/结构发送相关的确保图形命令和图形上下文被卸载并被调度用于消费的技术。

4. 发明申请

US20140198116A1 A METHOD AND DEVICE TO AUGMENT VOLATILE MEMORY IN A GRAPHICS SUBSYSTEM WITH NON-VOLATILE MEMORY 有权
标题翻译：具有非易失性存储器的图形子系统中的波动记忆体的方法和装置
公开(公告)号：US20140198116A1
公开(公告)日：2014-07-17
申请号：US13977261
申请日：2011-12-28
申请人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
发明人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
IPC分类号： G06T1/60
CPC分类号： G06T1/60 , G11C16/349
摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.
摘要翻译：描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。该方法还包括执行图形应用的图形处理器。图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

5. 发明授权

US09317892B2 Method and device to augment volatile memory in a graphics subsystem with non-volatile memory 有权
标题翻译：在具有非易失性存储器的图形子系统中增加易失性存储器的方法和装置
公开(公告)号：US09317892B2
公开(公告)日：2016-04-19
申请号：US13977261
申请日：2011-12-28
申请人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
发明人： Bryan E. Veal , Travis T. Schluessler , Murali Ramadoss , Balaji Vembu
IPC分类号： G09G5/39 , G06T1/60 , G11C16/34
CPC分类号： G06T1/60 , G11C16/349
摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.
摘要翻译：描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。该方法还包括执行图形应用的图形处理器。图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

6. 发明授权

US09304813B2 CPU independent graphics scheduler for performing scheduling operations for graphics hardware 有权
标题翻译： CPU独立的图形调度程序，用于执行图形硬件的调度操作
公开(公告)号：US09304813B2
公开(公告)日：2016-04-05
申请号：US13552122
申请日：2012-07-18
申请人： Balaji Vembu , Aditya Navale , Murali Ramadoss , David I. Standring , Kritika Bala
发明人： Balaji Vembu , Aditya Navale , Murali Ramadoss , David I. Standring , Kritika Bala
IPC分类号： G06F9/46 , G06F15/16 , G06F7/38 , G06F9/48
CPC分类号： G06F9/4881 , Y02D10/24
摘要： A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.
摘要翻译：本文描述了用于执行图形硬件的调度操作的计算设备。计算设备包括被配置为执行应用的中央处理单元（CPU）。计算设备还包括被配置为独立于CPU操作的图形调度器。图形调度器被配置为接收与在CPU上执行的应用程序的工作负载有关的工作队列，并且基于工作队列对多个图形引擎中的任何一个执行调度操作。

7. 发明申请

US20150277981A1 PRIORITY BASED CONTEXT PREEMPTION 有权
标题翻译：基于优先级的语境预测
公开(公告)号：US20150277981A1
公开(公告)日：2015-10-01
申请号：US14227692
申请日：2014-03-27
申请人： Hema C. Nalluri , Aditya Navale , Peter L. Doyle , Murali Ramadoss , Balaji Vembu , Jeffery S. Boles
发明人： Hema C. Nalluri , Aditya Navale , Peter L. Doyle , Murali Ramadoss , Balaji Vembu , Jeffery S. Boles
IPC分类号： G06F9/50 , G06T1/20
CPC分类号： G06F9/5038 , G06T1/20
摘要： Methods and apparatuses may prioritize the processing of high priority and low priority contexts submitted to a processing unit through separate high priority and low priority context submission ports. According to one embodiment, submission of a context to the low priority port causes contexts in progress to be preempted, whereas submission of a context to the high priority port causes contexts in progress to be paused.
摘要翻译：方法和设备可以优先处理通过单独的高优先级和低优先级上下文提交端口提交给处理单元的高优先级和低优先权上下文。根据一个实施例，向低优先级端口提交上下文导致正在进行的上下文被抢占，而向高优先级端口提交上下文导致正在进行的上下文被暂停。

8. 发明申请

US20090172331A1 Securing content for playback 审中-公开
标题翻译：保护播放内容
公开(公告)号：US20090172331A1
公开(公告)日：2009-07-02
申请号：US12006282
申请日：2007-12-31
申请人： Balaji Vembu , Aditya Sreenivas , Wishwesh Gandhi , Sathyamurthi Sadhasivan , Gary Graunke , Scott Janus , Murali Ramadoss
发明人： Balaji Vembu , Aditya Sreenivas , Wishwesh Gandhi , Sathyamurthi Sadhasivan , Gary Graunke , Scott Janus , Murali Ramadoss
IPC分类号： G06F21/00
CPC分类号： G06F21/84 , G06F21/10 , G06F21/74
摘要： A graphics engine may include a decryption device, a renderer, and a sprite or overlay engine, all connected to a display. A memory may have a protected and non-protected portions in one embodiment. An application may store encrypted content on the non-protected portion of said memory. The decryption device may access the encrypted material, decrypt the material, and provide it to the renderer engine of a graphics engine. The graphics engine may then process the decrypted material using the protected portion of the memory. Only graphics devices can access the protected portion of the memory in at least one mode, preventing access by outside sources. In addition, the protected memory may be stolen memory that is not identified to the operating system, making that stolen memory inaccessible to applications running on the operating system.
摘要翻译：图形引擎可以包括全部连接到显示器的解密设备，渲染器和子画面或覆盖引擎。在一个实施例中，存储器可以具有受保护和非保护部分。应用可以将加密的内容存储在所述存储器的非保护部分上。解密设备可以访问加密的材料，解密材料，并将其提供给图形引擎的渲染器引擎。然后，图形引擎可以使用存储器的受保护部分来处理解密的材料。只有图形设备才能以至少一种模式访问存储器的受保护部分，从而防止外部源的访问。此外，受保护的存储器可能是未被识别到操作系统的被盗存储器，使得被盗的存储器不能在操作系统上运行的应用程序访问。

9. 发明授权

US09678795B2 Direct ring 3 submission of processing jobs to adjunct processors 有权
公开(公告)号：US09678795B2
公开(公告)日：2017-06-13
申请号：US13993089
申请日：2011-12-30
申请人： Altug Koker , Aditya Navale , Balaji Vembu , Murali Ramadoss
发明人： Altug Koker , Aditya Navale , Balaji Vembu , Murali Ramadoss
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48 , G06F15/167 , G06F9/54 , G06F12/14
CPC分类号： G06F9/50 , G06F9/4812 , G06F9/545 , G06F12/1491 , G06F15/167
摘要： Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

10. 发明申请

US20170091989A1 Position Only Shader Context Submission Through a Render Command Streamer 审中-公开
公开(公告)号：US20170091989A1
公开(公告)日：2017-03-30
申请号：US14865933
申请日：2015-09-25
申请人： Murali Ramadoss , Balaji Vembu , Hema C. Nalluri , Michael Apodaca , Jeffery S. Boles
发明人： Murali Ramadoss , Balaji Vembu , Hema C. Nalluri , Michael Apodaca , Jeffery S. Boles
IPC分类号： G06T15/80 , G06T1/20
CPC分类号： G06T15/80 , G06F9/48 , G06F9/4881 , G06T1/20
摘要： By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式