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    • 3. 发明授权
      US6047117A Diffusion-based method and apparatus for determining circuit interconnect voltage response 失效
    • Diffusion-based method and apparatus for determining circuit interconnect voltage response
    • 用于确定电路互连电压响应的基于扩散的方法和装置
    • US6047117A
    • 2000-04-04
    • US838091
    • 1997-04-15
    • Andrew B. Kahng , Sudhakar Muddu
    • Andrew B. Kahng , Sudhakar Muddu
    • G06F17/50 , G06G7/48
    • G06F17/5036 , G06G7/48
    • Disclosed is a diffusion-equation-based method of determining the time-domain response of an IC interconnect to an input voltage signal. Time-dependent voltage response determinations are accomplished analytically in the Laplace domain, with appropriate boundary conditions, treating the voltage response as a superposition of transmitted and reflected diffusions, based on parasitics as known quantities per unit length. The voltage response is thus determined by summing distinct reflected diffusions originating at both sides of the interconnect. The analysis proceeds on the assumption that only a selected small number of reflective components--normally only four--are required for sufficient accuracy. Voltage response from a sequence of interconnects is determined by treating the voltage response from the first interconnect as the input to the second, and repeating such looping with successive interconnects. A final inverse transform may be accomplished to express the response in the time domain. The method is limited to implementation on a computer, and an appropriately programmed computer comprises the apparatus of the invention.
    • 公开了一种基于扩散方程的方法，用于确定IC互连对输入电压信号的时域响应。 时间依赖性电压响应确定在拉普拉斯域解析地完成，具有适当的边界条件，根据作为每单位长度已知数量的寄生效应，将电压响应作为传输和反射扩散的叠加来处理。 因此，电压响应通过将源于互连的两侧的不同的反射扩散相加来确定。 假设只有选定的少量反射组件（通常只有4个）需要足够的精度才能进行分析。 通过将来自第一互连的电压响应作为输入到第二互连来确定来自一系列互连的电压响应，并且用连续互连重复这种循环。 可以完成最终的逆变换以在时域中表达响应。 该方法限于在计算机上的实现，并且适当编程的计算机包括本发明的装置。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US06389581B1 Optimizing repeaters positioning along interconnects 有权
    • Optimizing repeaters positioning along interconnects
    • 优化中继器沿互连定位
    • US06389581B1
    • 2002-05-14
    • US09388938
    • 1999-09-02
    • Sudhakar Muddu , Egino Sarto
    • Sudhakar Muddu , Egino Sarto
    • G06F1750
    • G06F17/505 , G06F17/5022
    • An aspect of interconnect design for optimizing delay characteristics of interconnects. The interconnect design for delay characteristics optimization is performed using a method for optimizing repeaters positioning along interconnects. The method includes inserting repeaters in positions along a first interconnect at predetermined intervals that are related to signals transition time. The method further includes inserting repeaters in positions along a second interconnect at the predetermined intervals, the second interconnect being a neighbor of the first interconnect. The positions of repeaters along the second interconnect are offset, by a predetermined length, relative to the positions of repeaters along the first interconnect so that the repeaters positions along the second interconnect are shifted relative to the repeaters positions along the first interconnect. In one embodiment, the predetermined length is half (0.5) of the predetermined interval such that repeaters are shifted by half, wherein the interconnect delay that corresponds to the offsetting by half of the predetermined interval minimizes the interconnect delay under worst case conditions. The repeaters are inserted to decrease interconnect delay and make the interconnect delay scale linearly with an interconnect length.
    • 用于优化互连延迟特性的互连设计的一个方面。 用于延迟特性优化的互连设计是使用一种用于优化沿着互连的中继器定位的方法来执行的。 该方法包括以与信号转换时间相关的预定间隔沿着第一互连的位置插入中继器。 该方法还包括以预定间隔将中继器插入沿着第二互连的位置，第二互连是第一互连的邻居。 沿着第二互连的转发器的位置相对于沿着第一互连的中继器的位置偏移预定长度，使得沿着第二互连的中继器位置相对于沿着第一互连的中继器位置移位。 在一个实施例中，预定长度是预定间隔的一半（0.5），使得中继器偏移一半，其中对应于预定间隔的一半的对应的互连延迟使最坏情况条件下的互连延迟最小化。 插入中继器以减少互连延迟，并使互连延迟按互连长度线性化。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06732065B1 Noise estimation for coupled RC interconnects in deep submicron integrated circuits 有权
    • Noise estimation for coupled RC interconnects in deep submicron integrated circuits
    • 深亚微米集成电路中耦合RC互连的噪声估计
    • US06732065B1
    • 2004-05-04
    • US09301863
    • 1999-04-29
    • Sudhakar Muddu
    • Sudhakar Muddu
    • G06F1710
    • G06F17/5036
    • Noise estimation for coupled interconnects in deep submicron integrated circuits. One aspect of the invention is a method for interconnect coupling noise estimation. Another aspect of the invention is a computer readable medium embodying computer program code. The computer program code is configured to cause a computer to perform steps for estimating the interconnect coupling noise. The interconnect coupling noise estimation (hereafter noise estimation) includes modeling a circuit. The circuit includes a pair of interconnects, each interconnect connecting a driver gate to a load gate, where signal activity at a first interconnect of the pair of interconnects is having an impact on a second interconnect of the pair of interconnects. The circuit modeling includes modeling the first and second interconnects, driver gates, and load gates. Driver gates are modeled using a voltage source driving a resistance. Load gates are modeled using a capacitance. The noise estimation further includes expressing transfer characteristics of the modeled circuit for one of or, each one at a time, for a plurality of input voltages including step and ramp input voltages. Additionally, the noise estimation includes expressing a voltage at the second interconnect based on the transfer characteristics. The transfer characteristics are expressed in view of a capacitive coupling between the first and second interconnects. The voltage represents the impact on the second interconnect that is in the form of interconnect coupling noise. The noise estimation also includes determining a peak value of the interconnect coupling noise from the expression for the voltage at the second interconnect. The interconnect coupling noise reaches a peak at a time determined for one of or, each one at a time, for both of the step and ramp input voltages.
    • 深亚微米集成电路中耦合互连的噪声估计。 本发明的一个方面是用于互连耦合噪声估计的方法。 本发明的另一方面是体现计算机程序代码的计算机可读介质。 计算机程序代码被配置为使计算机执行用于估计互连耦合噪声的步骤。 互连耦合噪声估计（以下称为噪声估计）包括对电路进行建模。 该电路包括一对互连，每个互连将驱动器栅极连接到负载栅极，其中该对互连件的第一互连处的信号活动对该对互连的第二互连具有影响。 电路建模包括对第一和第二互连，驱动器门和负载门进行建模。 使用驱动电阻的电压源对驱动器门进行建模。 负载门使用电容进行建模。 噪声估计进一步包括为包括步进和斜坡输入电压的多个输入电压表示模拟电路的传输特性，或者每一个一个。 此外，噪声估计包括基于传输特性来表现第二互连处的电压。 考虑到第一和第二互连之间的电容耦合来表示传输特性。 电压表示对互连耦合噪声形式的第二互连的影响。 噪声估计还包括从第二互连处的电压的表达式确定互连耦合噪声的峰值。 互连耦合噪声在步进电平和斜坡输入电压两者中为一个或每个时间确定的时间达到峰值。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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