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1. 发明授权

US09166567B2 Data-retained power-gating circuit and devices including the same 有权
标题翻译：数据保持功率门控电路和包括其的器件
公开(公告)号：US09166567B2
公开(公告)日：2015-10-20
申请号：US14210892
申请日：2014-03-14
申请人： Bong Il Park , Andrew B. Kahng , Seok Hyeong Kang , Jae Gon Lee
发明人： Bong Il Park , Andrew B. Kahng , Seok Hyeong Kang , Jae Gon Lee
IPC分类号： G05F1/10 , G05F3/02 , H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356008
摘要： A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.
摘要翻译：提供电源门控电路及包括其的装置。电源门控电路包括触发器，其被配置为接收第一电源电压和门控时钟信号以进行操作;以及开关电路，其连接在被配置为提供第一电源电压的第一电源电压源和第二电源电压电压源被配置为提供第二电源电压。开关电路包括第一开关，其被配置为连接在第一电源电压源和第二电源电压源之间并且响应于时钟使能信号而工作;第二开关被配置为连接在第一电源电压源和第二电源电压源，并响应于第一电源电压而工作。

2. 发明授权

US08949768B2 Standard cells having transistors annotated for gate-length biasing 有权
标题翻译：具有用于栅极长度偏置的晶体管的标准单元
公开(公告)号：US08949768B2
公开(公告)日：2015-02-03
申请号：US13620669
申请日：2012-09-14
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081 , G06F17/5063 , G06F17/5068 , G06F2217/78
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.
摘要翻译：公开了一种标准细胞库。标准单元库包含其中注释至少一个单元中的至少一个晶体管用于栅长度偏置的单元。栅极长度偏置包括栅极长度的修改，以便改变修改的栅极长度的速度或功率消耗。标准单元库是用于制造半导体器件（例如，作为半导体芯片的结果）的方法，通过制造在几何形状的一个或多个布局上限定的特征。注释用于在使用用于制造半导体器件的几何形状之前识别哪些晶体管栅极特征将被修改。

3. 发明授权

US08490043B2 Standard cells having transistors annotated for gate-length biasing 失效
公开(公告)号：US08490043B2
公开(公告)日：2013-07-16
申请号：US12717887
申请日：2010-03-04
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5063 , G06F17/5068 , G06F2217/78
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

4. 发明申请

US20130014073A1 STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING 失效
公开(公告)号：US20130014073A1
公开(公告)日：2013-01-10
申请号：US13620690
申请日：2012-09-14
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5063 , G06F17/5068 , G06F2217/78
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

5. 发明授权

US07676772B1 Layout description having enhanced fill annotation 失效
标题翻译：具有增强填充注释的布局描述
公开(公告)号：US07676772B1
公开(公告)日：2010-03-09
申请号：US11486936
申请日：2006-07-13
申请人： O. Samuel Nakagawa , Andrew B. Kahng , Pakman Wong
发明人： O. Samuel Nakagawa , Andrew B. Kahng , Pakman Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Computer readable media hosting a layout description of electric circuitry that includes a description of prospective fill units and includes characteristic data noting at least one characteristic of each fill unit. In one preferred embodiment, each prospective fill unit includes just a single prospective fill element. Also, in a preferred embodiment, said characteristic data includes effect on electrical characteristics of nearby electrical circuitry. These electrical characteristics may further include timing characteristics and capacitance characteristics. The effect on the thickness of nearby connective elements also may be noted.
摘要翻译：托管电路的布局描述的计算机可读介质，其包括预期填充单元的描述，并且包括注意每个填充单元的至少一个特性的特征数据。在一个优选实施例中，每个预期填充单元仅包括单个预期填充元素。此外，在优选实施例中，所述特征数据包括对附近电路的电特性的影响。这些电气特性还可以包括定时特性和电容特性。也可以注意对附近结缔组织的厚度的影响。

6. 发明授权

US08756555B2 Standard cells having transistors annotated for gate-length biasing 失效
公开(公告)号：US08756555B2
公开(公告)日：2014-06-17
申请号：US13620690
申请日：2012-09-14
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5063 , G06F17/5068 , G06F2217/78
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

7. 发明授权

US08635583B2 Standard cells having transistors annotated for gate-length biasing 有权
标题翻译：具有用于栅极长度偏置的晶体管的标准单元
公开(公告)号：US08635583B2
公开(公告)日：2014-01-21
申请号：US13620681
申请日：2012-09-14
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F17/5063 , G06F17/5081 , G06F2217/78 , H01L27/0207 , H01L27/11807
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.
摘要翻译：公开了一种标准细胞库。标准单元库包含其中注释至少一个单元中的至少一个晶体管用于栅长度偏置的单元。栅极长度偏置包括栅极长度的修改，以便改变修改的栅极长度的速度或功率消耗。标准单元库是用于制造半导体器件（例如，作为半导体芯片的结果）的方法，通过制造在几何形状的一个或多个布局上限定的特征。注释用于在使用用于制造半导体器件的几何形状之前识别哪些晶体管栅极特征将被修改。

8. 发明申请

US20130254734A1 Standard Cells having transistors annotated for gate-length biasing 审中-公开
标题翻译：具有用于栅极长度偏置的注入晶体管的标准单元
公开(公告)号：US20130254734A1
公开(公告)日：2013-09-26
申请号：US13620669
申请日：2012-09-14
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5063 , G06F17/5068 , G06F2217/78
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.
摘要翻译：公开了一种标准细胞库。标准单元库包含其中注释至少一个单元中的至少一个晶体管用于栅长度偏置的单元。栅极长度偏置包括栅极长度的修改，以便改变修改的栅极长度的速度或功率消耗。标准单元库是用于制造半导体器件（例如，作为半导体芯片的结果）的方法，通过制造在几何形状的一个或多个布局上限定的特征。注释用于在使用用于制造半导体器件的几何形状之前识别哪些晶体管栅极特征将被修改。

9. 发明授权

US08402396B2 Layout decomposition for double patterning lithography 有权
标题翻译：双图案平版印刷的布局分解
公开(公告)号：US08402396B2
公开(公告)日：2013-03-19
申请号：US12892371
申请日：2010-09-28
申请人： Andrew B. Kahng , Hailong Yao
发明人： Andrew B. Kahng , Hailong Yao
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/70
摘要： The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.
摘要翻译：本发明提供用于布局分解以产生可用于进行双重图案化光刻（DPL）的曝光布局的系统和方法。本发明的优选实施方案由计算机执行，并提供使用整数线性规划（ILP）制剂的用于双重图案化光刻（DPL）的布局分解的替代方法。考虑到有助于传统DPL技术的成本的上述方面，本发明的实施例满足了关键的优化目标，即降低布局分解的总成本。本发明的实施例提供了用于优化DPL布局分解的整数线性规划（ILP），相位冲突检测（PCD）和节点选择二进制（NBD）公式，具有避免小的慢跑线端的过程感知成本函数，以及最大化多边形分割点的重叠。成本函数也可以在着陆垫，连接点和长运行中进行优先分割。

10. 发明申请

US20130014071A1 STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING 有权
标题翻译：具有栅格长度偏移的晶体管的标准电池
公开(公告)号：US20130014071A1
公开(公告)日：2013-01-10
申请号：US13620681
申请日：2012-09-14
申请人： Puneet Gupta , Andrew B. Kahng
发明人： Puneet Gupta , Andrew B. Kahng
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5063 , G06F17/5081 , G06F2217/78 , H01L27/0207 , H01L27/11807
摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.
摘要翻译：公开了一种标准细胞库。标准单元库包含其中注释至少一个单元中的至少一个晶体管用于栅长度偏置的单元。栅极长度偏置包括栅极长度的修改，以便改变修改的栅极长度的速度或功率消耗。标准单元库是用于制造半导体器件（例如，作为半导体芯片的结果）的方法，通过制造在几何形状的一个或多个布局上限定的特征。注释用于在使用用于制造半导体器件的几何形状之前识别哪些晶体管栅极特征将被修改。

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