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1. 发明授权

US08872946B2 Systems and methods for raw image processing 有权
标题翻译：原始图像处理的系统和方法
公开(公告)号：US08872946B2
公开(公告)日：2014-10-28
申请号：US13485056
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , David Hayward , Simon Wolfenden Butler , Joseph Anthony Petolino, Jr. , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , David Hayward , Simon Wolfenden Butler , Joseph Anthony Petolino, Jr. , Joseph P. Bratt
IPC分类号： H04N5/217
CPC分类号： H04N5/217 , H04N5/2176 , H04N5/357
摘要： Systems and methods for processing raw image data are provided. One example of such a system may include memory to store image data in raw format from a digital imaging device and an image signal processor to process the image data. The image signal processor may include data conversion logic and a raw image processing pipeline. The data conversion logic may convert the image data into a signed format to preserve negative noise from the digital imaging device. The raw image processing pipeline may at least partly process the image data in the signed format. The raw image processing pipeline may also include, among other things, black level compensation logic, fixed pattern noise reduction logic, temporal filtering logic, defective pixel correction logic, spatial noise filtering logic, lens shading correction logic, and highlight recovery logic.
摘要翻译：提供了处理原始图像数据的系统和方法。这种系统的一个示例可以包括存储器，以存储来自数字成像设备的原始格式的图像数据和图像信号处理器来处理图像数据。图像信号处理器可以包括数据转换逻辑和原始图像处理流水线。数据转换逻辑可以将图像数据转换为带符号格式以保护来自数字成像装置的负噪声。原始图像处理流水线可以至少部分地以签名格式处理图像数据。原始图像处理流水线还可以包括黑电平补偿逻辑，固定图案噪声降低逻辑，时间滤波逻辑，缺陷像素校正逻辑，空间噪声滤波逻辑，透镜阴影校正逻辑和高亮恢复逻辑。

2. 发明授权

US5928355A Apparatus for reducing instruction issue stage stalls through use of a staging register 失效
标题翻译：用于通过使用分段寄存器来减少指令发布阶段停顿的装置
公开(公告)号：US5928355A
公开(公告)日：1999-07-27
申请号：US884272
申请日：1997-06-27
申请人： Joseph Anthony Petolino, Jr.
发明人： Joseph Anthony Petolino, Jr.
IPC分类号： G06F9/38
CPC分类号： G06F9/3875 , G06F9/3836 , G06F9/3838
摘要： The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued from an instruction queue to the next stage of the pipeline by providing such information at a point early in the machine cycle.
摘要翻译：本发明通过将指令的发布从它们的发送中分离出来到它们各自的流水线中来解决与现有技术相关的问题。这允许通过在机器周期的早期提供这样的信息来确定特定指令是否可以安全地从指令队列发出到管线的下一阶段。

3. 发明授权

US5838946A Method and apparatus for accomplishing processor read of selected information through a cache memory 失效
标题翻译：用于通过高速缓存存储器来完成对所选信息的处理器读取的方法和装置
公开(公告)号：US5838946A
公开(公告)日：1998-11-17
申请号：US523217
申请日：1995-09-05
申请人： Joseph Anthony Petolino, Jr.
发明人： Joseph Anthony Petolino, Jr.
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0888
摘要： The present invention provides for a method and apparatus for reading non-cachable information in a cache memory system. The cache memory system includes a processor, a buffer, a multiplexor, main memory, an input/output unit, a cache controller, a memory management unit, and cache memory. In a read operation, the processor directs a read operation specifying a first address to the cache memory. The cache controller initially determines whether the information desired is cachable or non-cachable. If the information desired is determined to be non-cachable, the cache controller causes any information presently contained in a first location in the cache memory to be stored in the buffer. In the interim, the cache controller causes the memory management unit to initiate an access of the information desired from the first address. Once accessed, this information is temporarily written into the first location within the cache memory. From this first location within the cache memory, the information is coupled, as desired, to the processor. The cache controller then restores the information formerly in the first location, by coupling the contents of the buffer back into the first location within the cache memory.
摘要翻译：本发明提供一种用于在高速缓冲存储器系统中读取不可高速缓存的信息的方法和装置。高速缓冲存储器系统包括处理器，缓冲器，多路复用器，主存储器，输入/输出单元，高速缓存控制器，存储器管理单元和高速缓冲存储器。在读取操作中，处理器将指定第一地址的读取操作指向高速缓冲存储器。缓存控制器最初确定所需信息是可高速缓存还是不可高速缓存。如果所要求的信息被确定为不可高速缓存，则高速缓存控制器使当前包含在高速缓冲存储器中的第一位置的信息存储在缓冲器中。在此期间，高速缓存控制器使存储器管理单元启动对从第一地址所期望的信息的访问。一旦访问，该信息被暂时写入高速缓冲存储器内的第一位置。从高速缓冲存储器内的该第一位置，信息根据需要耦合到处理器。然后，高速缓存控制器通过将缓冲器的内容返回到高速缓冲存储器内的第一位置来恢复先前在第一位置的信息。

4. 发明授权

US09743057B2 Systems and methods for lens shading correction 有权
公开(公告)号：US09743057B2
公开(公告)日：2017-08-22
申请号：US13485235
申请日：2012-05-31
申请人： Guy Cote , Joseph Anthony Petolino, Jr. , Suk Hwan Lim , D. Amnon Silverstein
发明人： Guy Cote , Joseph Anthony Petolino, Jr. , Suk Hwan Lim , D. Amnon Silverstein
IPC分类号： H04N5/14 , H04N5/232 , H04N5/365 , H04N5/367 , H04N9/04 , H04N9/73 , H04N9/64
CPC分类号： H04N9/64 , H04N5/142 , H04N5/23229 , H04N5/23254 , H04N5/365 , H04N5/367 , H04N9/045 , H04N9/735
摘要： Systems and methods for correcting intensity drop-offs due to geometric properties of lenses are provided. In one example, a method includes receiving an input pixel of the image data, the image data acquired using an image sensor. A color component of the input pixel is determined. A gain grid is determined by pointing to the gain grid in external memory. Each of the plurality of grid points is associated with a lens shading gain selected based upon the color of the input pixel. A nearest set of grid points that enclose the input pixel is identified. Further, a lens shading gain is determined by interpolating the lens shading gains associated with each of the set of grid points and is applied to the input pixel.

5. 发明授权

US5918034A Method for decoupling pipeline stages 失效
标题翻译：去耦管道阶段的方法
公开(公告)号：US5918034A
公开(公告)日：1999-06-29
申请号：US884273
申请日：1997-06-27
申请人： Joseph Anthony Petolino, Jr.
发明人： Joseph Anthony Petolino, Jr.
IPC分类号： G06F9/38 , G06F9/312 , G06F9/315
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3867
摘要： The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued from an instruction queue to the next stage of the pipeline by providing such information at a point early in the machine cycle. In a multistage pipeline, a first stage is bypassed to provide instructions to a second stage regardless of the ability of the first stage to store the instruction from the instruction issuing unit.
摘要翻译：本发明通过将指令的发布从它们的发送中分离出来到它们各自的流水线中来解决与现有技术相关的问题。这允许通过在机器周期的早期提供这样的信息来确定特定指令是否可以安全地从指令队列发出到管线的下一阶段。在多级流水线中，绕过第一级以向第二级提供指令，而与第一级存储来自指令发出单元的指令的能力无关。

6. 发明授权

US5958041A Latency prediction in a pipelined microarchitecture 失效
标题翻译：流水线微体系结构中的延迟预测
公开(公告)号：US5958041A
公开(公告)日：1999-09-28
申请号：US883416
申请日：1997-06-26
申请人： Joseph Anthony Petolino, Jr. , William Lee Lynch , Gary Raymond Lauterbach , Chitresh Chandra Narasimhaiah
发明人： Joseph Anthony Petolino, Jr. , William Lee Lynch , Gary Raymond Lauterbach , Chitresh Chandra Narasimhaiah
IPC分类号： G06F9/312 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： The present invention solves the problems associated with the prior art by providing a latency prediction bit (LPB) to indicate the latency with which an instruction should be executed, implicitly indicating whether a data dependency is likely to exist and the likelihood of that dependency causing a hazard. In a processor according to the present invention, an instruction dependent upon a given LDI instruction is issued a given number of machine cycles after that LDI instruction, the number of machine cycles being based on the value of the LPB associated with that LDI instruction. The LPB's value, in turn, depends on whether data will need to be forwarded to the functional unit involved during the execution of LDI instruction. The ability to predict such hazards is important in maintaining a pipeline's throughput and avoiding unnecessary recirculations.
摘要翻译：本发明通过提供等待时间预测位（LPB）来解决与现有技术相关的问题，以指示应该执行指令的等待时间，隐含地指示数据依赖性是否可能存在，并且该依赖性的可能性导致冒险。在根据本发明的处理器中，依赖于给定的LDI指令的指令在该LDI指令之后被给定给定数量的机器周期，机器周期数是基于与该LDI指令相关联的LPB的值。 LPB的值反过来取决于在执行LDI指令期间是否需要将数据转发到所涉及的功能单元。预测这种危害的能力对于维持管道的吞吐量并避免不必要的再循环是重要的。

7. 发明授权

US5898852A Load instruction steering in a dual data cache microarchitecture 失效
标题翻译：在双数据缓存微体系结构中加载指令转向
公开(公告)号：US5898852A
公开(公告)日：1999-04-27
申请号：US883639
申请日：1997-06-26
申请人： Joseph Anthony Petolino, Jr. , William Lee Lynch , Gary Raymond Lauterbach , Kalon S. Holdbrook
发明人： Joseph Anthony Petolino, Jr. , William Lee Lynch , Gary Raymond Lauterbach , Kalon S. Holdbrook
IPC分类号： G06F9/312 , G06F9/38 , G06F9/06
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3832 , G06F9/3853 , G06F9/3885
摘要： An apparatus for executing an instruction is provided. The instruction loads data into one of a plurality of registers in a register file and is in a first group of instructions. A second group of instructions is executed sequentially after the first group of instructions. The first and second groups of instructions should each include at least one instruction. The apparatus includes a first memory, a second memory, a first functional unit coupled to the first memory, and a second functional unit coupled to the first memory and to the second memory. The first and second functional units are both capable of executing the instruction. Also included is an instruction issue unit coupled to the first and the second functional units. The instruction issue unit issues the instruction to a selected functional unit selected from one of the first and the second functional units. This selection is based on a load prediction bit associated with the instruction.
摘要翻译：提供了一种用于执行指令的装置。该指令将数据加载到寄存器文件中的多个寄存器之一并且处于第一组指令中。在第一组指令之后顺序地执行第二组指令。第一组和第二组指令应分别包含至少一条指令。该装置包括第一存储器，第二存储器，耦合到第一存储器的第一功能单元和耦合到第一存储器和第二存储器的第二功能单元。第一和第二功能单元都能执行指令。还包括耦合到第一和第二功能单元的指令发布单元。指令发布单元向从第一和第二功能单元之一中选择的所选功能单元发出指令。该选择基于与指令相关联的负载预测位。

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