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1. 发明授权

US06882230B2 System and method for control parameter re-centering in a controlled phase lock loop system 有权
标题翻译：控制参数重心在控制锁相环系统中的系统和方法
公开(公告)号：US06882230B2
公开(公告)日：2005-04-19
申请号：US10604095
申请日：2003-06-26
申请人： Joseph A. Iadanza , Ram Kelkar , Stephen D. Wyatt
发明人： Joseph A. Iadanza , Ram Kelkar , Stephen D. Wyatt
IPC分类号： H03L7/18 , H03L7/00
CPC分类号： H03L7/18 , H03L2207/06
摘要： A re-centering system (116) for re-centering the control parameter of a phase lock loop (PLL) (112). The re-centering system includes sources (140) for obtaining/storing operating parameters, such as environmental data (184), setup data (188), and other knowns data (192). At least one state machine (132) utilizes the operating parameters to adjust the topology of the PLL so as to achieve a desirable topology for each target output frequency (18) that substantially centers the performance envelope(s) (120, 124, 128) to a desired pre-selected value of the control parameter. The re-centering system also includes a comparator (136) for comparing measured values of the control parameter to a pre-selected value. The state machine utilizes the output of the comparator to substantially center the corresponding performance envelope at the pre-selected value.
摘要翻译：一种用于重新定心锁相环（PLL）（112）的控制参数的重定心系统（116）。再定心系统包括用于获取/存储诸如环境数据（184），建立数据（188）和其他已知数据（192）的操作参数的源（140）。至少一个状态机（132）利用操作参数来调整PLL的拓扑结构，以便实现基本上使性能包络（120,124,128）中心的每个目标输出频率（18）的理想拓扑，到控制参数的期望的预选值。重新定心系统还包括比较器（136），用于将控制参数的测量值与预选值进行比较。状态机利用比较器的输出使相应的性能包络大致居中在预先选定的值。

2. 发明授权

US5541442A Integrated compact capacitor-resistor/inductor configuration 失效
标题翻译：集成紧凑型电容电阻/电感器配置
公开(公告)号：US5541442A
公开(公告)日：1996-07-30
申请号：US298685
申请日：1994-08-31
申请人： Richard F. Keil , Ram Kelkar , Ilya I. Novof , Jeffery H. Oppold , Kenneth D. Short , Stephen D. Wyatt
发明人： Richard F. Keil , Ram Kelkar , Ilya I. Novof , Jeffery H. Oppold , Kenneth D. Short , Stephen D. Wyatt
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/00
CPC分类号： H01L27/08
摘要： An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor. This second layer of metal may also be used to form inductors. Moreover both inductors and resistors can be formed; however this may require a third layer of metal for connection purposes.
摘要翻译：提供了由FET技术形成的电容器和电阻器和/或导体的改进配置。在该配置中，形成电容器，其中衬底的扩散区被用作电容器的一个板，并且通常将FET的栅电极用作电容器的另一个板，两个板被分离通过常规的薄介电栅极氧化物层。诸如二氧化硅的绝缘体覆盖栅电极，并且通过绝缘体制造到栅电极和扩散区的电连接，以允许电容器的两个板根据需要连接到各种装置或部件。该绝缘层的顶表面也用于形成金属电阻。根据所需电阻的值，可以使用第二绝缘层，并且使用第二级金属来连接形成在第一金属层上的电阻器的部分，以形成更长的电阻。该第二层金属也可用于形成电感器。此外，可以形成电感器和电阻器; 然而，这可能需要用于连接目的的第三层金属。

3. 发明授权

US5491439A Method and apparatus for reducing jitter in a phase locked loop circuit 失效
标题翻译：减少锁相环电路抖动的方法和装置
公开(公告)号：US5491439A
公开(公告)日：1996-02-13
申请号：US298695
申请日：1994-08-31
申请人： Ram Kelkar , Ilya I Novof , Stephen D. Wyatt
发明人： Ram Kelkar , Ilya I Novof , Stephen D. Wyatt
IPC分类号： H03D13/00 , H03K3/0231 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10 , H03L7/06
CPC分类号： H03L7/095 , H03K3/0231 , H03L7/0893 , H03D13/004 , H03L2207/06 , H03L7/0896 , H03L7/0898 , Y10S331/02
摘要： A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
摘要翻译：锁相环电路包括相位/频率检测器，该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

4. 发明授权

US5525932A Lock indicator for phase locked loop circuit 失效
标题翻译：锁相环电路锁定指示灯
公开(公告)号：US5525932A
公开(公告)日：1996-06-11
申请号：US298621
申请日：1994-08-31
申请人： Ram Kelkar , Iiya I. Novof , Stephen D. Wyatt
发明人： Ram Kelkar , Iiya I. Novof , Stephen D. Wyatt
IPC分类号： H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10
CPC分类号： H03L7/095 , H03L7/0893 , H03L7/0896 , Y10S331/02
摘要： A phase locked loop circuit which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone" is provided. A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has a voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
摘要翻译：提供了一种锁相环电路，其包括使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲的相位/频率检测器。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

5. 发明授权

US5513225A Resistorless phase locked loop circuit employing direct current injection 失效
标题翻译：采用直流注入的无电阻锁相环电路
公开(公告)号：US5513225A
公开(公告)日：1996-04-30
申请号：US298632
申请日：1994-08-31
申请人： Ram Kelkar , Ilya I. Novof , Donald E. Strayer , Stephen D. Wyatt
发明人： Ram Kelkar , Ilya I. Novof , Donald E. Strayer , Stephen D. Wyatt
IPC分类号： H03L7/093 , H03L7/089 , H03L7/095 , H03L7/099 , H03L7/10 , H03D3/24
CPC分类号： H03L7/0995 , H03L7/0893 , H03L7/095 , H03L2207/06 , H03L7/0896 , H03L7/0898
摘要： A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition. The circuits for these components are described in detail.
摘要翻译：锁相环电路包括相位/频率检测器，该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。详细描述这些部件的电路。

6. 发明授权

US07532040B1 Programmable sensitivity frequency coincidence detection circuit and method 失效
标题翻译：可编程灵敏度频率一致检测电路及方法
公开(公告)号：US07532040B1
公开(公告)日：2009-05-12
申请号：US11928080
申请日：2007-10-30
申请人： Ram Kelkar , Grant P. Kesselring
发明人： Ram Kelkar , Grant P. Kesselring
IPC分类号： G01R23/02
CPC分类号： G01R23/005 , H03D13/001
摘要： A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.
摘要翻译：一种用于检测多个周期数字信号中的每一个的频率边缘的频率一致检测电路。电路产生每个周期性数字信号的计数指示器，并将每个计数指示器与可编程灵敏度输入进行比较，以确定每个周期性数字信号中的相应一个的一致窗口。电路确定符合窗口的信号重合。在另一个实施例中，提供了一种频率一致检测方法。该方法检测多个周期性数字信号中的每一个的频率边缘，为每个周期性数字信号产生计数指示符，并将每个计数指示符与可编程灵敏度输入进行比较，以确定每个周期数字信号中的每一个的相应窗口周期性数字信号。该方法确定符合窗口的信号重合。

7. 发明授权

US07378890B2 Programmable low-power high-frequency divider 有权
公开(公告)号：US07378890B2
公开(公告)日：2008-05-27
申请号：US11857632
申请日：2007-09-19
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K23/52 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/667
摘要： Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

8. 发明授权

US07075350B2 Programmable low-power high-frequency divider 失效
公开(公告)号：US07075350B2
公开(公告)日：2006-07-11
申请号：US11070730
申请日：2005-03-02
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/356
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.

9. 发明授权

US07049864B2 Apparatus and method for high frequency state machine divider with low power consumption 失效
标题翻译：具有低功耗的高频状态机分频器的装置和方法
公开(公告)号：US07049864B2
公开(公告)日：2006-05-23
申请号：US10710115
申请日：2004-06-18
申请人： Ram Kelkar , Pradeep Thiagarajan
发明人： Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K21/00
CPC分类号： G06F1/04 , G06F1/025
摘要： A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.
摘要翻译：数字分频装置包括多个下一状态发生器元件，其接收输入时钟信号，并且被配置为为相应的多个内部状态变量中的每一个生成下一个值。多个触发器元件被配置为存储针对多个内部状态变量的所生成的下一个值，所述多个触发器元件还被配置为向下一个状态发生器提供多个内部状态变量的当前值元件通过它们之间的反馈路径。所生成的多个内部状态变量的下一个值基于多个内部状态变量和输入时钟信号的当前值。

10. 发明申请

US20050280449A1 APPARATUS AND METHOD FOR HIGH FREQUENCY STATE MACHINE DIVIDER WITH LOW POWER CONSUMPTION 失效
标题翻译：低功耗高频状态机分路器的装置和方法
公开(公告)号：US20050280449A1
公开(公告)日：2005-12-22
申请号：US10710115
申请日：2004-06-18
申请人： Ram Kelkar , Pradeep Thiagarajan
发明人： Ram Kelkar , Pradeep Thiagarajan
IPC分类号： G06F1/025 , G06F1/04 , H03K21/00
CPC分类号： G06F1/04 , G06F1/025
摘要： A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.
摘要翻译：数字分频装置包括多个下一状态发生器元件，其接收输入时钟信号，并且被配置为为相应的多个内部状态变量中的每一个生成下一个值。多个触发器元件被配置为存储针对多个内部状态变量的所生成的下一个值，所述多个触发器元件还被配置为向下一个状态发生器提供多个内部状态变量的当前值元件通过它们之间的反馈路径。所生成的多个内部状态变量的下一个值基于多个内部状态变量和输入时钟信号的当前值。

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