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1. 发明授权

US07412584B2 Data alignment micro-architecture systems and methods 失效
标题翻译：数据对齐微架构系统和方法
公开(公告)号：US07412584B2
公开(公告)日：2008-08-12
申请号：US10838078
申请日：2004-05-03
申请人： Jose S. Niell , Gilbert M. Wolrich , Thomas L. Dmukauskas , Mark B. Rosenbluth
发明人： Jose S. Niell , Gilbert M. Wolrich , Thomas L. Dmukauskas , Mark B. Rosenbluth
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3816 , G06F9/3842 , G06F12/04
摘要： Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an indication to the shifter of an amount by which the data is to be shifted. In one embodiment, the control logic provides support for speculative execution. The control logic may also permit multiplexing of big endian and little endian data alignment operations, and/or multiplexing of data alignment operations with non-data alignment operations. In one embodiment, the memory unit, shifter, and control logic are integrated within a processing unit, such as a microengine in a network processor.
摘要翻译：公开了用于在存储器访问和其他应用中对准数据的系统和方法。在一个实施例中，提供了一种系统，其包括存储器单元，移位器和可操作以将数据从存储器单元路由到移位器的控制逻辑，并向移位器发送数据要被移位的量的指示。在一个实施例中，控制逻辑提供对推测执行的支持。控制逻辑还可以允许大端和小端数据对准操作的复用，和/或数据对准操作与非数据对准操作的复用。在一个实施例中，存储器单元，移位器和控制逻辑集成在处理单元内，诸如网络处理器中的微引擎。

2. 发明申请

US20080022175A1 Program memory having flexible data storage capabilities 审中-公开
标题翻译：具有灵活数据存储功能的程序存储器
公开(公告)号：US20080022175A1
公开(公告)日：2008-01-24
申请号：US11478393
申请日：2006-06-29
申请人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert M. Wolrich , Jose S. Niell
发明人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert M. Wolrich , Jose S. Niell
IPC分类号： G01R31/28
CPC分类号： G06F9/3802 , G06F9/30043 , G06F9/342 , G06F9/3824 , G06F9/3851
摘要： A method according to one embodiment may include performing one or more fetch operations to retrieve one or more instructions from a program memory; scheduling a write instruction to write data from at least one data register into the program memory; and stealing one or more cycles from one or more of the fetch operations to write the data in the at least one data register into the program memory. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括执行一个或多个提取操作以从程序存储器检索一个或多个指令; 调度写指令以将数据从至少一个数据寄存器写入程序存储器; 以及从一个或多个获取操作中窃取一个或多个周期，以将所述至少一个数据寄存器中的数据写入程序存储器。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

3. 发明授权

US07555630B2 Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit 失效
标题翻译：用于在处理器单元中的多线程处理元件之间提供有效通信的方法和装置
公开(公告)号：US07555630B2
公开(公告)日：2009-06-30
申请号：US11018579
申请日：2004-12-21
申请人： Sanjeev Jain , Gilbert M. Wolrich , Mark B. Rosenbluth
发明人： Sanjeev Jain , Gilbert M. Wolrich , Mark B. Rosenbluth
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F13/4252
摘要： A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element.
摘要翻译：上下文转发总线在具有多个处理元件的处理器单元中有效地传送处理元件之间的控制和数据。控制和数据信息通过第一总线从处理元件传送到处理元件。

4. 发明授权

US06973550B2 Memory access control 失效
标题翻译：内存访问控制
公开(公告)号：US06973550B2
公开(公告)日：2005-12-06
申请号：US10264092
申请日：2002-10-02
申请人： Mark B. Rosenbluth , Gilbert M. Wolrich , Debra Bernstein , Richard Guerin
发明人： Mark B. Rosenbluth , Gilbert M. Wolrich , Debra Bernstein , Richard Guerin
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16
CPC分类号： G06F13/1642
摘要： In general, in one aspect, the disclosure describes storing identification of one or more memory buckets associated with different, respective, queued write commands, and, based on the stored identification, determining whether at least one bucket associated with a read command is included in one or more buckets associated with at least one queued write command.
摘要翻译：通常，在一个方面，本公开描述了存储与不同的，相应的排队的写入命令相关联的一个或多个存储器桶的标识，并且基于所存储的标识，确定与读取命令相关联的至少一个桶是否包括在与至少一个排队的写入命令相关联的一个或多个存储桶。

5. 发明授权

US09632782B2 Method and apparatus to process SHA-2 secure hashing algorithm 有权
公开(公告)号：US09632782B2
公开(公告)日：2017-04-25
申请号：US13976274
申请日：2012-03-30
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30 , G06F21/60 , H04L9/06 , H04L9/32
CPC分类号： G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30145 , G06F9/3802 , G06F9/384 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , H04L9/0643 , H04L9/3239 , H04L2209/125
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

6. 发明授权

US09292548B2 Digest generation 有权
标题翻译：消化一代
公开(公告)号：US09292548B2
公开(公告)日：2016-03-22
申请号：US13995236
申请日：2011-11-01
申请人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
发明人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
IPC分类号： G06F17/30
CPC分类号： G06F17/30303 , G06F17/30306 , G06F17/3033
摘要： In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.
摘要翻译：在一个实施例中，电路可以生成待组合的摘要以产生散列值。摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

7. 发明授权

US09092645B2 Efficient multiplication, exponentiation and modular reduction implementations 有权
标题翻译：有效的乘法，乘法和模块化削减实现
公开(公告)号：US09092645B2
公开(公告)日：2015-07-28
申请号：US13994782
申请日：2011-12-05
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： H04L29/00 , G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

8. 发明申请

US20150082047A1 EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS 有权
标题翻译：有效的实施，授权和模块化的减少实施
公开(公告)号：US20150082047A1
公开(公告)日：2015-03-19
申请号：US13994782
申请日：2011-12-05
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

9. 发明授权

US08953785B2 Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor 有权
标题翻译： 128位处理器上的SKEIN256 SHA3算法指令集
公开(公告)号：US08953785B2
公开(公告)日：2015-02-10
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

10. 发明申请

US20140237218A1 SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION FOR MULTI-PRECISION ARITHMETIC 有权
标题翻译：用于多精度算术的SIMD整数多项式累积指令
公开(公告)号：US20140237218A1
公开(公告)日：2014-08-21
申请号：US13992728
申请日：2011-12-19
申请人： Vinodh Gopal , Gilbert M. Wolrich , Erdinc Ozturk , James D. Guilford , Kirk S. Yap , Sean M. Gulley , wajdi K. Feghali , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Erdinc Ozturk , James D. Guilford , Kirk S. Yap , Sean M. Gulley , wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30101 , G06F9/3893
摘要： A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.
摘要翻译：乘法和累加（MAC）指令允许有效执行无符号整数乘法。 MAC指令表示作为第一操作数的第一向量寄存器，作为第二操作数的第二向量寄存器和作为目的地的第三向量寄存器。第一向量寄存器存储第一因子，第二向量寄存器存储部分和。执行MAC指令以将第一因子与隐式第二因子相乘以生成乘积，并将部分和添加到乘积以生成结果。第一个因素，隐含的第二个因子和部分和具有相同的数据宽度，产品的数据宽度是两倍。结果的最大一半存储在第三向量寄存器中，结果的最低有效半存储在第二向量寄存器中。

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