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1. 发明授权

US07500204B2 Real-time adaptive control for best IC performance 有权
标题翻译：实时自适应控制，实现最佳的IC性能
公开(公告)号：US07500204B2
公开(公告)日：2009-03-03
申请号：US10559208
申请日：2004-05-28
申请人： Jose De Jesus Pineda De Gyvez , Francesco Pessolano , Rinze Ida Mechitildis Peter Meijer , Josep Rius Vazquez , Kiran Batni Raghavendra Rao
发明人： Jose De Jesus Pineda De Gyvez , Francesco Pessolano , Rinze Ida Mechitildis Peter Meijer , Josep Rius Vazquez , Kiran Batni Raghavendra Rao
IPC分类号： G06F17/50 , G06F1/00
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into different islands (30). Each island (30) is controlled and its working conditions are modified depending on some parameters. The remainder of the chip is controlled as well, depending on other parameters. This requires that each island (30) has a local controller (36) communicating with a global controller (42). The main control parameters are e.g. supply voltage, threshold voltage and clock frequency.
摘要翻译：本发明涉及用于最佳集成电路（IC）性能的实时自适应控制。适应行为是在当地进行的。系统被划分成不同的岛屿（30）。每个岛（30）被控制，并且其工作条件根据一些参数而被修改。芯片的其余部分也受到控制，取决于其他参数。这要求每个岛（30）具有与全局控制器（42）通信的本地控制器（36）。主要控制参数是例如。电源电压，阈值电压和时钟频率。

2. 发明授权

US07336088B2 Method and apparatus for determining IDDQ 失效
标题翻译：用于确定IDDQ的方法和装置
公开(公告)号：US07336088B2
公开(公告)日：2008-02-26
申请号：US10528253
申请日：2003-08-08
申请人： Josep Rius Vazquez , Jose De Jesus Pineda De Gyvez
发明人： Josep Rius Vazquez , Jose De Jesus Pineda De Gyvez
IPC分类号： G01R31/02
CPC分类号： G01R31/3008 , G01R31/3004
摘要： A test apparatus for testing a device under test (DUT) to detect a defect comprises a measurement circuit (ME), a threshold circuit (TH), and a control circuit (CG). The measurement circuit (ME) comprises a counter (C1) which counts clock pulses (OLK) during a count period (TC) to obtain a counted number (N) of clock pulses (CLK). The count period (TC) has a start determined by the start (tl) of a testing cycle which occurs at the instant a switch (S) which is coupled to an terminal (IN) of the device under test (DUT) removes a power supply voltage (VDD) from the terminal (IN) and the voltage (VDD′) at the terminal (IN) starts decaying. An end of the count period (TC) is determined by an instant (t2) a comparator (COM1) detects that the voltage (VDD′) at the terminal (IN) crosses a reference value (VREF). The control circuit (CG) generates the clock signal (CLK) and/or a reference number (NTH) taking into account the variability of the manufacturing process of the circuit under test (CUT). The threshold circuit (TH) generates a pass/fail signal (PF) by comparing the counted number (N) and the reference number (NTH).
摘要翻译：用于测试被测设备（DUT）以检测缺陷的测试装置包括测量电路（ME），阈值电路（TH）和控制电路（CG）。测量电路（ME）包括在计数周期（TC）期间计数时钟脉冲（OLK）的计数器（C 1），以获得计时数（N）的时钟脉冲（CLK）。计数周期（TC）具有由耦合到被测器件（DUT）的开关（S）（DUT）的瞬间发生的测试周期的开始（t1）确定的开始，该开关（S）端子（IN）的电源电压（VDD）和端子（IN）的电压（VDD'）开始衰减。计数周期（TC）的结束由比较器（COM 1）检测到端子（IN）处的电压（VDD'）与参考值（VREF）相交的时刻（t 2）确定。考虑到被测电路（CUT）的制造过程的可变性，控制电路（CG）产生时钟信号（CLK）和/或参考号（NTH）。阈值电路（TH）通过比较计数（N）和参考数（NTH）来产生通过/失败信号（PF）。

3. 发明授权

US07886259B2 Method and circuit arrangement for determining power supply noise 有权
标题翻译：用于确定电源噪声的方法和电路布置
公开(公告)号：US07886259B2
公开(公告)日：2011-02-08
申请号：US10546395
申请日：2004-02-12
申请人： Josep Rius Vazquez , Jose De Jesus Pineda De Gyvez
发明人： Josep Rius Vazquez , Jose De Jesus Pineda De Gyvez
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used as an indicator of the power supply noise. Thereby, a real-time power supply noise monitoring can be carried out at any point of a power distribution network of an observed circuitry.
摘要翻译：本发明涉及一种用于确定配电网络的电源噪声的方法和电路装置。通过测量由配电网供电的延迟电路的传播延迟来确定电源噪声，其中测量步骤的结果用作电源噪声的指标。因此，可以在观察电路的配电网络的任何点处执行实时电源噪声监测。

4. 发明授权

US07457971B2 Monitoring and controlling power consumption in a sequential logic circuit 有权
标题翻译：监控和控制顺序逻辑电路中的功耗
公开(公告)号：US07457971B2
公开(公告)日：2008-11-25
申请号：US10558090
申请日：2004-05-17
申请人： Jose de Jesus Pineda De Gyvez , Josep Rius Vazquez
发明人： Jose de Jesus Pineda De Gyvez , Josep Rius Vazquez
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： H03K19/0016 , H03K19/215
摘要： The present invention relates to an electronic circuit, apparatus and method for monitoring and controlling power consumption. Accordingly, there is provided an electronic circuit, apparatus and method that includes one or more sequential logic elements (12) that are capable of receiving a clock signal (CLK) and an input signal (I) and providing an output signal (O). The sequential logic element (12) further comprises circuitry (20) for monitoring the input and output signals (I, O), and providing a control signal (CS) in response to the input and output signals (I, O), wherein the IC's power consumption is operatively controllable in response to the control signal.
摘要翻译：本发明涉及用于监视和控制功耗的电子电路，装置和方法。因此，提供了一种电子电路，装置和方法，其包括能够接收时钟信号（CLK）和输入信号（I）并提供输出信号（O）的一个或多个顺序逻辑元件（12）。顺序逻辑元件（12）还包括用于监测输入和输出信号（I，O）以及响应于输入和输出信号（I，O）提供控制信号（CS）的电路（20），其中 IC的功耗响应于控制信号而可操作地控制。

5. 发明申请

US20060123368A1 Real-time adaptive control for best ic performance 有权
标题翻译：实时自适应控制，实现最佳的ic性能
公开(公告)号：US20060123368A1
公开(公告)日：2006-06-08
申请号：US10559208
申请日：2004-05-28
申请人： Jose Pineda De Gyvez , Francesco Pessolano , Rinze Meijer , Josep Rius Vazquez , Kiran Rao
发明人： Jose Pineda De Gyvez , Francesco Pessolano , Rinze Meijer , Josep Rius Vazquez , Kiran Rao
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into different islands (30). Each island (30) is controlled and its working conditions are modified depending on some parameters. The remainder of the chip is controlled as well, depending on other parameters. This requires that each island (30) has a local controller (36) communicating with a global controller (42). The main control parameters are e.g. supply voltage, threshold voltage and clock frequency.
摘要翻译：本发明涉及用于最佳集成电路（IC）性能的实时自适应控制。适应行为是在当地进行的。系统被划分成不同的岛屿（30）。每个岛（30）被控制，并且其工作条件根据一些参数而被修改。芯片的其余部分也受到控制，取决于其他参数。这要求每个岛（30）具有与全局控制器（42）通信的本地控制器（36）。主要控制参数是例如。电源电压，阈值电压和时钟频率。

6. 发明授权

US08138783B2 Testable integrated circuit and IC test method 有权
标题翻译：可测试集成电路和IC测试方法
公开(公告)号：US08138783B2
公开(公告)日：2012-03-20
申请号：US12440448
申请日：2007-09-04
申请人： Josep Rius Vazquez , Luis Elvira Villagra , Rinze I. M. P. Meijer
发明人： Josep Rius Vazquez , Luis Elvira Villagra , Rinze I. M. P. Meijer
IPC分类号： G01R31/02
CPC分类号： G01R31/3008
摘要： A circuit portion (100) of an IC comprises a plurality of conductive tracks (130) for coupling respective circuit portion elements (150), e.g. standard logic cells, to a power supply rail (110), with the conductive tracks (130) being coupled to the power supply rail (110) via at least one enable switch (132). The circuit portion (100) further comprising an element (160) for determining a voltage gradient over the circuit portion (100) in a test mode of the integrated circuit (600), which is conductively coupled to the conductive tracks (130). The element (160) has a first end portion (164) for coupling the element (160) to the power supply terminal and a second end portion (166) for coupling the element (160) to the output (620) in the test mode. This facilitates IDDQ testing of the circuit portion (100) by means of measuring a voltage gradient over the element (160).
摘要翻译： IC的电路部分（100）包括用于耦合各个电路部分元件（150）的多个导电轨道（130），例如，标准逻辑单元到达电源轨道（110），其中导电轨道（130）经由至少一个启用开关（132）耦合到电源轨道（110）。电路部分（100）还包括用于在集成电路（600）的测试模式中确定电路部分（100）上的电压梯度的元件（160），该电流部分导电地耦合到导电轨道（130）。元件（160）具有用于将元件（160）耦合到电源端子的第一端部（164）和用于在测试模式下将元件（160）耦合到输出（620）的第二端部（166）。这通过测量元件（160）上的电压梯度来促进电路部分（100）的IDDQ测试。

7. 发明申请

US20090315583A1 TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD 有权
标题翻译：可测试的集成电路和IC测试方法
公开(公告)号：US20090315583A1
公开(公告)日：2009-12-24
申请号：US12440448
申请日：2007-09-04
申请人： Josep Rius Vazquez , Luis Elvira Villagra , Rinze I.M.P. Meijer
发明人： Josep Rius Vazquez , Luis Elvira Villagra , Rinze I.M.P. Meijer
IPC分类号： G01R31/28 , H01L23/58
CPC分类号： G01R31/3008
摘要： A circuit portion (100) of an IC comprises a plurality of conductive tracks (130) for coupling respective circuit portion elements (150), e.g. standard logic cells, to a power supply rail (110), with the conductive tracks (130) being coupled to the power supply rail (110) via at least one enable switch (132). The circuit portion (100) further comprising an element (160) for determining a voltage gradient over the circuit portion (100) in a test mode of the integrated circuit (600), which is conductively coupled to the conductive tracks (130). The element (160) has a first end portion (164) for coupling the element (160) to the power supply terminal and a second end portion (166) for coupling the element (160) to the output (620) in the test mode. This facilitates IDDQ testing of the circuit portion (100) by means of measuring a voltage gradient over the element (160).
摘要翻译： IC的电路部分（100）包括用于耦合各个电路部分元件（150）的多个导电轨道（130），例如，标准逻辑单元到达电源轨道（110），其中导电轨道（130）经由至少一个启用开关（132）耦合到电源轨道（110）。电路部分（100）还包括用于在集成电路（600）的测试模式中确定电路部分（100）上的电压梯度的元件（160），该电流部分导电地耦合到导电轨道（130）。元件（160）具有用于将元件（160）耦合到电源端子的第一端部（164）和用于在测试模式下将元件（160）耦合到输出（620）的第二端部（166）。这通过测量元件（160）上的电压梯度来促进电路部分（100）的IDDQ测试。

8. 发明申请

US20060248354A1 Monitoring and controlling power consumption 有权
标题翻译：监控功耗
公开(公告)号：US20060248354A1
公开(公告)日：2006-11-02
申请号：US10558090
申请日：2004-05-17
申请人： Jose Pineda De Gyvez , Josep Rius Vazquez
发明人： Jose Pineda De Gyvez , Josep Rius Vazquez
IPC分类号： G06F1/00
CPC分类号： H03K19/0016 , H03K19/215
摘要： The present invention relates to an electronic circuit, apparatus and method for monitoring and controlling power consumption. Accordingly, there is provided an electronic circuit, apparatus and method that includes one or more sequential logic elements (12) that are capable of receiving a clock signal (CLK) and an input signal (I) and providing an output signal (O). The sequential logic element (12) further comprises circuitry (20) for monitoring the input and output signals (I, O), and providing a control signal (CS) in response to the input and output signals (I, O), wherein the IC's power consumption is operatively controllable in response to the control signal.
摘要翻译：本发明涉及用于监视和控制功耗的电子电路，装置和方法。因此，提供了一种电子电路，装置和方法，其包括能够接收时钟信号（CLK）和输入信号（I）并提供输出信号（O）的一个或多个顺序逻辑元件（12）。顺序逻辑元件（12）还包括用于监测输入和输出信号（I，O）以及响应于输入和输出信号（I，O）提供控制信号（CS）的电路（20），其中 IC的功耗响应于控制信号而可操作地控制。

9. 发明申请

US20060190878A1 Method and circuit arrangement for determining power supply noise 有权
标题翻译：用于确定电源噪声的方法和电路布置
公开(公告)号：US20060190878A1
公开(公告)日：2006-08-24
申请号：US10546395
申请日：2004-02-12
申请人： Josep Rius Vazquez , Jose Pineda De Gyvez
发明人： Josep Rius Vazquez , Jose Pineda De Gyvez
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022 , G06F17/5036
摘要： The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used as an indicator of the power supply noise. Thereby, a real-time power supply noise monitoring can be carried out at any point of a power distribution network of an observed circuitry.
摘要翻译：本发明涉及一种用于确定配电网络的电源噪声的方法和电路装置。通过测量由配电网供电的延迟电路的传播延迟来确定电源噪声，其中测量步骤的结果用作电源噪声的指标。因此，可以在观察电路的配电网络的任何点处执行实时电源噪声监测。

10. 发明申请

US20060250152A1 Method and apparatus for determining iddq 失效
标题翻译：用于确定iddq的方法和装置
公开(公告)号：US20060250152A1
公开(公告)日：2006-11-09
申请号：US10528253
申请日：2003-08-08
申请人： Josep Rius Vazquez , Jose Pineda De Gyvez
发明人： Josep Rius Vazquez , Jose Pineda De Gyvez
IPC分类号： G01R31/26
CPC分类号： G01R31/3008 , G01R31/3004
摘要： A test apparatus for testing a device under test (DUT) to detect a defect comprises a measurement circuit (ME), a threshold circuit (TH), and a control circuit (CG). The measurement circuit (ME) comprises a counter (C1) which counts clock pulses (CLK) during a count period (TC) to obtain a counted number (N) of clock pulses (CLK). The count period (TC) has a start determined by the start (t1) of a testing cycle which occurs at the instant a switch (S) which is coupled to an terminal (IN) of the device under test (DUT) removes a power supply voltage (VDD) from the terminal (IN) and the voltage (VDD′) at the terminal (IN) starts decaying. An end of the count period (TC) is determined by an instant (t2) a comparator (COM1) detects that the voltage (VDD′) at the terminal (IN) crosses a reference value (VREF). The control circuit (CG) generates the clock signal (CLK) and/or a reference number (NTH) taking into account the variability of the manufacturing process of the circuit under test (CUT). The threshold circuit (TH) generates a pass/fail signal (PF) by comparing the counted number (N) and the reference number (NTH).
摘要翻译：用于测试被测设备（DUT）以检测缺陷的测试装置包括测量电路（ME），阈值电路（TH）和控制电路（CG）。测量电路（ME）包括在计数周期（TC）期间计数时钟脉冲（CLK）的计数器（C 1），以获得计时数（N）的时钟脉冲（CLK）。计数周期（TC）具有由测试周期的开始（t 1）确定的开始，该测试周期发生在耦合到被测器件（DUT）的端子（IN）的开关（S）瞬间移除端子（IN）的电源电压（VDD）和端子（IN）的电压（VDD'）开始衰减。计数周期（TC）的结束由比较器（COM 1）检测到端子（IN）处的电压（VDD'）与参考值（VREF）相交的时刻（t 2）确定。考虑到被测电路（CUT）的制造过程的可变性，控制电路（CG）产生时钟信号（CLK）和/或参考号（NTH）。阈值电路（TH）通过比较计数（N）和参考数（NTH）来产生通过/失败信号（PF）。

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