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1. 发明授权

US08161349B2 Data parallelizing receiver 有权
标题翻译：数据并行接收器
公开(公告)号：US08161349B2
公开(公告)日：2012-04-17
申请号：US12183552
申请日：2008-07-31
申请人： Hoe-Ju Chung , Joo-Sun Choi , Ken S. Lim
发明人： Hoe-Ju Chung , Joo-Sun Choi , Ken S. Lim
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6575
摘要： Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.
摘要翻译：提供了一种数据并行接收器，包括用于从外部接收串行数据作为分组的输入信号接收器，对串行数据进行采样，以输入顺序对准采样数据，并将对准的数据转换为并行数据以输出并行数据，循环冗余检查（CRC）部分计算器，用于接收并行数据，根据输入顺序将并行数据分组成组，并对每个组执行部分CRC计算，以顺序输出多个部分CRC计算结果，以及CRC部分用于接收多个部分CRC计算结果的计算合并，并将部分CRC计算结果合并到输出CRC计算数据。

2. 发明授权

US07930492B2 Memory system having low power consumption 失效
标题翻译：具有低功耗的存储系统
公开(公告)号：US07930492B2
公开(公告)日：2011-04-19
申请号：US12006766
申请日：2008-01-04
申请人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
发明人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C7/1075
摘要： A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.
摘要翻译：存储器系统基于堆栈位置信息选择性地设置信令模式。存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。因此，存储系统具有降低的功耗。

3. 发明申请

US20080177949A1 Memory system having low power consumption 失效
标题翻译：具有低功耗的存储系统
公开(公告)号：US20080177949A1
公开(公告)日：2008-07-24
申请号：US12006766
申请日：2008-01-04
申请人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
发明人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
IPC分类号： G06F12/08
CPC分类号： G11C7/1075
摘要： A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.
摘要翻译：存储器系统基于堆栈位置信息选择性地设置信令模式。存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。因此，存储系统具有降低的功耗。

4. 发明授权

US07688666B2 Memory system for controlling power and method thereof 有权
标题翻译：用于控制电力的存储系统及其方法
公开(公告)号：US07688666B2
公开(公告)日：2010-03-30
申请号：US11896123
申请日：2007-08-29
申请人： Joo-Sun Choi , Hoe-Ju Chung
发明人： Joo-Sun Choi , Hoe-Ju Chung
IPC分类号： G11C5/14
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Example embodiments relate to a memory system and a method of controlling power thereof. The memory system may include a memory device and a memory controller. The memory device may be configured to be set to a specific power characteristic mode in response to a mode register set command so as to provide a power characteristic information corresponding to the specific power characteristic mode. The memory controller may be configured to provide the mode register set command to the memory device, configured to read the power characteristic information corresponding to the specific power characteristic mode from the memory device, configured to generate a power control information based on the power characteristic information, configured generate a command in response to the power control information, and provide the command to the memory device according to the power control information.
摘要翻译：示例性实施例涉及一种存储器系统及其功率控制方法。存储器系统可以包括存储器设备和存储器控制器。存储器件可以被配置为响应于模式寄存器设置命令被设置为特定功率特性模式，以便提供对应于特定功率特性模式的功率特性信息。存储器控制器可以被配置为向存储器件提供模式寄存器设置命令，被配置为从存储器件读取与特定功率特性模式相对应的功率特性信息，其被配置为基于功率特性信息生成功率控制信息配置为响应于功率控制信息生成命令，并且根据功率控制信息向存储器件提供命令。

5. 发明申请

US20080059822A1 Memory system for controlling power and method thereof 有权
标题翻译：用于控制电力的存储系统及其方法
公开(公告)号：US20080059822A1
公开(公告)日：2008-03-06
申请号：US11896123
申请日：2007-08-29
申请人： Joo-Sun Choi , Hoe-Ju Chung
发明人： Joo-Sun Choi , Hoe-Ju Chung
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Example embodiments relate to a memory system and a method of controlling power thereof. The memory system may include a memory device and a memory controller. The memory device may be configured to be set to a specific power characteristic mode in response to a mode register set command so as to provide a power characteristic information corresponding to the specific power characteristic mode. The memory controller may be configured to provide the mode register set command to the memory device, configured to read the power characteristic information corresponding to the specific power characteristic mode from the memory device, configured to generate a power control information based on the power characteristic information, configured generate a command in response to the power control information, and provide the command to the memory device according to the power control information.
摘要翻译：示例性实施例涉及一种存储器系统及其功率控制方法。存储器系统可以包括存储器设备和存储器控制器。存储器件可以被配置为响应于模式寄存器设置命令被设置为特定功率特性模式，以便提供对应于特定功率特性模式的功率特性信息。存储器控制器可以被配置为向存储器件提供模式寄存器设置命令，被配置为从存储器件读取与特定功率特性模式相对应的功率特性信息，其被配置为基于功率特性信息生成功率控制信息配置为响应于功率控制信息生成命令，并且根据功率控制信息向存储器件提供命令。

6. 发明授权

US08279652B2 Reconfigurable input/output in hierarchical memory link 有权
标题翻译：分层存储器链路中可重配置的输入/输出
公开(公告)号：US08279652B2
公开(公告)日：2012-10-02
申请号：US12708049
申请日：2010-02-18
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C7/10 , H01L2924/0002 , H01L2924/00
摘要： A memory system and memory module includes a plurality of memory devices, each having a plurality, e.g. four, ports for transmitting and receiving command signals, write data signals and read data signals. One of the memory devices is connected to a host or controller, and the remaining memories are connected together, typically by point-to-point links. When the memory system configuration is such that at least one of the ports in at least one of the memory devices is not used, one or more other ports can use the pins that may otherwise have been used by the unused ports. As a result, a set of reconfigurable, shared pins is defined in which two ports share the pins. The port that is not being used in a particular application for the memory device is not connected to the shared pins, and another port that is being used in the application is connected to the shared pins. This allows for the used of fewer package pins and, consequently, reduced package size.
摘要翻译：存储器系统和存储器模块包括多个存储器件，每个存储器件具有多个，例如，四个用于发送和接收命令信号的端口，写数据信号和读数据信号。其中一个存储设备连接到主机或控制器，其余存储器通常通过点对点链路连接在一起。当存储器系统配置使得至少一个存储器设备中的至少一个端口不被使用时，一个或多个其他端口可以使用另外可能由未使用的端口使用的引脚。因此，定义了一组可重新配置的共享引脚，其中两个端口共享引脚。在存储器件的特定应用中未使用的端口未连接到共享引脚，并且应用中正在使用的另一个端口连接到共享引脚。这允许使用更少的封装引脚，从而减少封装尺寸。

7. 发明申请

US20070106838A1 Apparatus and method for controlling refresh of semiconductor memory device 有权
标题翻译：用于控制半导体存储器件刷新的装置和方法
公开(公告)号：US20070106838A1
公开(公告)日：2007-05-10
申请号：US11504421
申请日：2006-08-15
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G06F13/28
CPC分类号： G06F13/1636 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C2211/4061
摘要： A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices. The refresh control circuit classifies the semiconductor memory devices into first and second groups and sets an auto refresh interval of the semiconductor memory devices belong to the first group and an auto refresh interval of the semiconductor memory devices belong to the second group different from each other.
摘要翻译：控制多个半导体存储器件的存储器控制器包括控制半导体存储器件的刷新操作的刷新控制电路。刷新控制电路将半导体存储器件分为第一组和第二组，并且设置属于第一组的半导体存储器件的自动刷新间隔，并且属于第二组的半导体存储器件的自动刷新间隔彼此不同。

8. 发明授权

US08817549B2 Integrated circuit memory device 有权
标题翻译：集成电路存储器件
公开(公告)号：US08817549B2
公开(公告)日：2014-08-26
申请号：US13478774
申请日：2012-05-23
申请人： Choong-Sun Shin , Joo-Sun Choi
发明人： Choong-Sun Shin , Joo-Sun Choi
IPC分类号： G11C7/10
CPC分类号： G11C5/04 , G11C5/025 , G11C7/10 , G11C8/12 , G11C11/408 , G11C11/4093 , G11C11/4097
摘要： A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2^K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.
摘要翻译：半导体存储器件包括形成在一个芯片上的多个存储器区域，每个存储器区域具有多个易失性存储器单元，其形成为2K比特的密度或容量，其中K是大于或等于的整数以及用于输入和输出易失性存储器单元的数据的多个输入/输出（I / O）端子，以及控制用于将数据写入存储区域的写入操作的至少一个外围区域，以及用于基于从外部输入的命令和地址从存储器区域读取数据。因此，存储区域的总体或整个密度对应于非标准（或“临时”）密度，使得半导体存储器件可具有临时密度。

9. 发明申请

US20110289269A1 MEMORY SYSTEM AND METHOD HAVING POINT-TO-POINT LINK 审中-公开
标题翻译：具有点对点链接的记忆系统和方法
公开(公告)号：US20110289269A1
公开(公告)日：2011-11-24
申请号：US13153850
申请日：2011-06-06
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G06F12/00
CPC分类号： G06F12/0802
摘要： A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.
摘要翻译：存储器系统包括用于产生控制信号的控制器和用于从控制器接收控制信号的主存储器。次存储器耦合到主存储器，辅存储器适于从主存储器接收控制信号。控制信号定义要由主存储器和次存储器之一执行的背景操作以及由另一个主存储器和次存储器执行的前景操作。主存储器和辅助存储器通过点对点链路连接。主存储器和次存储器之间的至少一个链路可以是至少部分序列化的链路。主存储器和次存储器中的至少一个可以包括机载内部高速缓冲存储器。

10. 发明申请

US20070097753A1 Memory device, memory system and method of inputting/outputting data into/from the same 有权
标题翻译：存储器件，存储器系统以及从其输入/输出数据的方法
公开(公告)号：US20070097753A1
公开(公告)日：2007-05-03
申请号：US11582290
申请日：2006-10-17
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock and prefetches K data from K memory cells connected to the activated word line and corresponds to the decoded column address, in response to a second clock, where a frequency of the second clock is 1/M of that of the first clock. The output buffer section outputs the K prefetched data as a data stream in response to a third clock. Therefore, a burden from the physical limit of the access speed may be alleviated when the data I/O speed is increased.
摘要翻译：存储器件包括存储单元阵列，行解码部分，K位预取部分和输出缓冲器部分。行解码部分响应于第一时钟解码行地址，以激活对应于解码的行地址的字线之一。 K位预取部分响应于第二时钟对列地址进行解码，并且响应于第二时钟从与连接到激活字线的K个存储器单元中的K个存储器单元相对应地对应于解码的列地址，第二个时钟是第一个时钟的1 / M。输出缓冲器部分响应于第三个时钟输出K个预取数据作为数据流。因此，当数据I / O速度增加时，可以减轻访问速度的物理限制的负担。

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