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1. 发明申请

US20080177949A1 Memory system having low power consumption 失效
标题翻译：具有低功耗的存储系统
公开(公告)号：US20080177949A1
公开(公告)日：2008-07-24
申请号：US12006766
申请日：2008-01-04
申请人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
发明人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
IPC分类号： G06F12/08
CPC分类号： G11C7/1075
摘要： A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.
摘要翻译：存储器系统基于堆栈位置信息选择性地设置信令模式。存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。因此，存储系统具有降低的功耗。

2. 发明授权

US07930492B2 Memory system having low power consumption 失效
标题翻译：具有低功耗的存储系统
公开(公告)号：US07930492B2
公开(公告)日：2011-04-19
申请号：US12006766
申请日：2008-01-04
申请人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
发明人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C7/1075
摘要： A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.
摘要翻译：存储器系统基于堆栈位置信息选择性地设置信令模式。存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。因此，存储系统具有降低的功耗。

3. 发明授权

US07688666B2 Memory system for controlling power and method thereof 有权
标题翻译：用于控制电力的存储系统及其方法
公开(公告)号：US07688666B2
公开(公告)日：2010-03-30
申请号：US11896123
申请日：2007-08-29
申请人： Joo-Sun Choi , Hoe-Ju Chung
发明人： Joo-Sun Choi , Hoe-Ju Chung
IPC分类号： G11C5/14
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Example embodiments relate to a memory system and a method of controlling power thereof. The memory system may include a memory device and a memory controller. The memory device may be configured to be set to a specific power characteristic mode in response to a mode register set command so as to provide a power characteristic information corresponding to the specific power characteristic mode. The memory controller may be configured to provide the mode register set command to the memory device, configured to read the power characteristic information corresponding to the specific power characteristic mode from the memory device, configured to generate a power control information based on the power characteristic information, configured generate a command in response to the power control information, and provide the command to the memory device according to the power control information.
摘要翻译：示例性实施例涉及一种存储器系统及其功率控制方法。存储器系统可以包括存储器设备和存储器控制器。存储器件可以被配置为响应于模式寄存器设置命令被设置为特定功率特性模式，以便提供对应于特定功率特性模式的功率特性信息。存储器控制器可以被配置为向存储器件提供模式寄存器设置命令，被配置为从存储器件读取与特定功率特性模式相对应的功率特性信息，其被配置为基于功率特性信息生成功率控制信息配置为响应于功率控制信息生成命令，并且根据功率控制信息向存储器件提供命令。

4. 发明申请

US20080059822A1 Memory system for controlling power and method thereof 有权
标题翻译：用于控制电力的存储系统及其方法
公开(公告)号：US20080059822A1
公开(公告)日：2008-03-06
申请号：US11896123
申请日：2007-08-29
申请人： Joo-Sun Choi , Hoe-Ju Chung
发明人： Joo-Sun Choi , Hoe-Ju Chung
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Example embodiments relate to a memory system and a method of controlling power thereof. The memory system may include a memory device and a memory controller. The memory device may be configured to be set to a specific power characteristic mode in response to a mode register set command so as to provide a power characteristic information corresponding to the specific power characteristic mode. The memory controller may be configured to provide the mode register set command to the memory device, configured to read the power characteristic information corresponding to the specific power characteristic mode from the memory device, configured to generate a power control information based on the power characteristic information, configured generate a command in response to the power control information, and provide the command to the memory device according to the power control information.
摘要翻译：示例性实施例涉及一种存储器系统及其功率控制方法。存储器系统可以包括存储器设备和存储器控制器。存储器件可以被配置为响应于模式寄存器设置命令被设置为特定功率特性模式，以便提供对应于特定功率特性模式的功率特性信息。存储器控制器可以被配置为向存储器件提供模式寄存器设置命令，被配置为从存储器件读取与特定功率特性模式相对应的功率特性信息，其被配置为基于功率特性信息生成功率控制信息配置为响应于功率控制信息生成命令，并且根据功率控制信息向存储器件提供命令。

5. 发明授权

US08161349B2 Data parallelizing receiver 有权
标题翻译：数据并行接收器
公开(公告)号：US08161349B2
公开(公告)日：2012-04-17
申请号：US12183552
申请日：2008-07-31
申请人： Hoe-Ju Chung , Joo-Sun Choi , Ken S. Lim
发明人： Hoe-Ju Chung , Joo-Sun Choi , Ken S. Lim
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6575
摘要： Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.
摘要翻译：提供了一种数据并行接收器，包括用于从外部接收串行数据作为分组的输入信号接收器，对串行数据进行采样，以输入顺序对准采样数据，并将对准的数据转换为并行数据以输出并行数据，循环冗余检查（CRC）部分计算器，用于接收并行数据，根据输入顺序将并行数据分组成组，并对每个组执行部分CRC计算，以顺序输出多个部分CRC计算结果，以及CRC部分用于接收多个部分CRC计算结果的计算合并，并将部分CRC计算结果合并到输出CRC计算数据。

6. 发明授权

US08112680B2 System and device with error detection/correction process and method outputting data 有权
标题翻译：具有错误检测/校正处理和方法输出数据的系统和设备
公开(公告)号：US08112680B2
公开(公告)日：2012-02-07
申请号：US12044183
申请日：2008-03-07
申请人： Hoe-Ju Chung , Jung-Bae Lee
发明人： Hoe-Ju Chung , Jung-Bae Lee
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G11C5/02 , G11C5/04 , G11C7/02 , G11C7/1006 , G11C7/1045 , G11C2029/0411 , H04L1/0041 , H04L1/0057
摘要： A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.
摘要翻译：系统，设备和相关方法用于经由包括所选择的数据通道的多个数据通道来传送数据。在第一操作模式中，经由包括所选择的数据通道的多个数据通道来传送有效载荷数据和相关的补充数据。在第二种操作模式中，只有有效载荷数据经由多个数据通道被传送，除了所选择的数据通道。

7. 发明授权

US07447862B2 Memory system and timing control method of the same 有权
标题翻译：存储系统和时序控制方法相同
公开(公告)号：US07447862B2
公开(公告)日：2008-11-04
申请号：US10886926
申请日：2004-07-08
申请人： Jung-Bae Lee , Hoe-Ju Chung
发明人： Jung-Bae Lee , Hoe-Ju Chung
IPC分类号： G06F13/42
CPC分类号： G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C2207/2254
摘要： A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.
摘要翻译：存储器系统包括至少一个存储器模块，每个存储器模块具有用于产生模式数据的模式数据产生电路，该模式数据具有共同应用命令信号的多个存储器，并且分别应用相应的数据; 以及存储器控制器，用于分别将命令信号和相应的数据应用于多个存储器，在定时控制操作期间向存储器模块应用模式数据产生命令，使用以下方式计算到达多个存储器中的每一个的数据之间的时间差：从每个存储器输出的图案数据，并使用计算出的数据到达时间差来接收和输出数据。因此，在存储器控制器和存储器之间实现稳定的数据传输。

8. 发明申请

US20070271424A1 Memory module, a memory system including a memory controller and a memory module and methods thereof 失效
标题翻译：存储器模块，包括存储器控制器和存储器模块的存储器系统及其方法
公开(公告)号：US20070271424A1
公开(公告)日：2007-11-22
申请号：US11723821
申请日：2007-03-22
申请人： Jung-Bae Lee , Hoe-Ju Chung
发明人： Jung-Bae Lee , Hoe-Ju Chung
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device. An example read operation may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal and an address from the received packet command if the received packet command corresponds to a read operation, transferring the extracted command signal and address to at least one memory device, receiving read data corresponding to the extracted command signal and address from the at least one memory device via write/read data lines internal to the given one memory unit and transmitting the received read data from the interface via read data lines external to the given one memory unit.
摘要翻译：存储器模块，包括存储器控制器和存储器模块的存储器系统及其方法。示例性存储器模块可以包括多个存储单元，每个存储器单元具有接口和至少一个存储器件。示例性写入操作方法可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，提取命令信号，地址和写入数据如果接收到的分组命令对应于写入操作，则接收到的分组命令，通过给定一个存储器单元内部的写入/读取数据线将提取的写入数据传送到至少一个存储器件，并将传送的写入数据写入至少一个存储设备。示例性读取操作可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，从接收到的分组命令中提取命令信号和地址如果接收的分组命令对应于读取操作，则将所提取的命令信号和地址传送到至少一个存储器件，通过内部的写入/读取数据线从至少一个存储器件接收与所提取的命令信号和地址相对应的读取数据到给定的一个存储器单元，并且通过给定的一个存储器单元外部的读取数据线从接口发送接收到的读取数据。

9. 发明申请

US20050010741A1 Memory system and timing control method of the same 有权
标题翻译：内存系统和时序控制方法相同
公开(公告)号：US20050010741A1
公开(公告)日：2005-01-13
申请号：US10886926
申请日：2004-07-08
申请人： Jung-Bae Lee , Hoe-Ju Chung
发明人： Jung-Bae Lee , Hoe-Ju Chung
IPC分类号： G11C7/00 , G06F12/02 , G06F13/16 , G11C7/10 , G11C7/22
CPC分类号： G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C2207/2254
摘要： A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.
摘要翻译：存储器系统包括至少一个存储器模块，每个存储器模块具有用于产生模式数据的模式数据产生电路，该模式数据具有共同应用命令信号的多个存储器，并且分别应用相应的数据; 以及存储器控制器，用于分别将命令信号和相应的数据应用于多个存储器，在定时控制操作期间向存储器模块应用模式数据产生命令，使用以下方式计算到达多个存储器中的每一个的数据之间的时间差：从每个存储器输出的图案数据，并使用计算出的数据到达时间差来接收和输出数据。因此，在存储器控制器和存储器之间实现稳定的数据传输。

10. 发明授权

US08654864B2 System and method for selectively performing single-ended and differential signaling 有权
标题翻译：用于选择性地执行单端和差分信号的系统和方法
公开(公告)号：US08654864B2
公开(公告)日：2014-02-18
申请号：US13775543
申请日：2013-02-25
申请人： Hoe-Ju Chung , Jung-Bae Lee
发明人： Hoe-Ju Chung , Jung-Bae Lee
IPC分类号： H04B14/06
CPC分类号： H04L25/0264 , H04L25/0272
摘要： In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.
摘要翻译：在通信系统中，使用单端或差分信令有选择地发送数据。相对于具有不同相对相位的多个时钟信号发送数据。当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

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