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1. 发明授权

US6052305A Erasing circuit for a flash memory device having a triple well structure 有权
标题翻译：具有三重阱结构的闪存器件的擦除电路
公开(公告)号：US6052305A
公开(公告)日：2000-04-18
申请号：US143409
申请日：1998-08-28
申请人： Tae Hum Yang , Joo Young Kim , Young Dong Joo , Jong Bae Jeong , Jong Seuk Lee , Il Hyun Choi , Mun Pyo Hong , Chae Hyun Jung
发明人： Tae Hum Yang , Joo Young Kim , Young Dong Joo , Jong Bae Jeong , Jong Seuk Lee , Il Hyun Choi , Mun Pyo Hong , Chae Hyun Jung
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16
摘要： The present invention discloses a flash memory device, a first well and second well are formed in a substrate, a plurality of memory cell are formed in the second well and arranged in an array having a multiplicity of bit lines and word lines. Voltage is applied to the first well and second well, respectively, with time interval so that an over erasing of the memory cell and lowering of cycling characteristic can be prevented.
摘要翻译：本发明公开了一种闪速存储器件，第一阱和第二阱形成在衬底中，多个存储单元形成在第二阱中并且布置成具有多个位线和字线的阵列。电压分别以时间间隔施加到第一阱和第二阱，使得可以防止存储单元的过度擦除和循环特性的降低。

2. 发明授权

US5946233A Flash memory device having word line latch for multi-bit programming 失效
标题翻译：具有用于多位编程的字线锁存器的闪存器件
公开(公告)号：US5946233A
公开(公告)日：1999-08-31
申请号：US99365
申请日：1998-06-18
申请人： Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee , Young Dong Joo
发明人： Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee , Young Dong Joo
IPC分类号： G11C13/00 , G11C16/10 , G11C16/06
CPC分类号： G11C16/10
摘要： This invention relates to a flash memory device capable of performing a multi bit program by sequentially supplying a data stored on a data storage circuit to a word line coupled to a select gate of a memory cell selected by a row decoder when a program bias voltage is applied to a bit line.
摘要翻译：本发明涉及一种闪速存储器件，其能够通过在存储在数据存储电路上的数据上顺序提供耦合到由行解码器所选择的存储单元的选择栅极的字线执行多位程序，当程序偏置电压为应用于位线。

3. 发明授权

US5894438A Method for programming and erasing a memory cell of a flash memory device 失效
标题翻译：用于编程和擦除闪速存储器件的存储单元的方法
公开(公告)号：US5894438A
公开(公告)日：1999-04-13
申请号：US105589
申请日：1998-06-26
申请人： Tae Hum Yang , Young Dong Joo , Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee
发明人： Tae Hum Yang , Young Dong Joo , Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/14
摘要： The present invention provides a method for programming and erasing a plurality of flash memory cells simultaneously while the power consumptions for those operations are significantly reduced, and the method for programming a memory cell of a flash memory device, wherein the memory cell is formed on a P-well surrounded by an N-well of a semiconductor substrate, including the steps of: applying a negative voltage to a control gate of the memory cell; applying a positive voltage to a drain of the memory cell; applying a positive voltage to the P-well, wherein the voltage is the same as or lower than the voltage applied to the drain; applying a power supply voltage to the N-well; and leaving a source of the memory cell uncoupled, wherein the steps are performed either in sequence or at random.
摘要翻译：本发明提供了一种用于在显着减少用于这些操作的功耗的同时同时编程和擦除多个闪存单元的方法，以及用于对闪存设备的存储单元进行编程的方法，其中存储单元形成在 P阱由半导体衬底的N阱包围，包括以下步骤：向存储单元的控制栅极施加负电压; 对存储单元的漏极施加正电压; 向P阱施加正电压，其中电压与施加到漏极的电压相同或者更低; 向N阱施加电源电压; 并且将所述存储器单元的源离开，其中所述步骤按顺序或随机地执行。

4. 发明申请

US20120069682A1 WORD LINE BOOSTER FOR FLASH MEMORY DEVICE 有权
标题翻译：用于闪存存储器的WORD线路保护器
公开(公告)号：US20120069682A1
公开(公告)日：2012-03-22
申请号：US12259040
申请日：2008-10-27
申请人： Young Dong Joo
发明人： Young Dong Joo
IPC分类号： G11C16/08
CPC分类号： G11C16/30 , G11C16/08
摘要： A nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with the specific voltage as a drive voltage during an operation of the memory device, wherein the word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel each other adapted to generate a boosting voltage and a first precharge circuit for precharging the first boosting capacitor and the second boosting capacitor. the word line booster circuit further includes a third boosting capacitor operatively connected to the first boosting capacitor and the second boosting capacitor via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor when the charge sharing transistor is enabled. In addition, the word line booster circuit includes a high voltage detector to generate a detecting signal in response to a control signal from an address transition detector and the output signal generated by the third boosting capacitor and load resistor and a clock control circuit adapted to enable the charge sharing transistor and to disable one of the first boosting capacitor and the second boosting capacitor upon receiving the control signal from the address transition detector and the detecting signal from the voltage detector. The word line booster circuit further includes a discharge circuit to discharge the boosting voltage at a node connected to the third boosting capacitor.
摘要翻译：非易失性存储器件包括存储器单元的行和列的阵列以及与存储器单元相关联的多个字线和位线。所述存储装置还包括与所述字线耦合的字线升压电路，用于在所述存储器件的操作期间将所选择的字线提供特定电压作为驱动电压，其中所述字线升压电路包括第一升压电容器和彼此并联连接的第二升压电容器，用于产生升压电压;以及第一预充电电路，用于对第一升压电容器和第二升压电容器进行预充电。字线升压电路还包括经由电荷共享晶体管可操作地连接到第一升压电容器和第二升压电容器的第三升压电容器，第三升压电容器连接到负载电阻器的一端，以在第当电荷共享晶体管使能时，负载电阻的另一端。此外，字线升压电路包括高电压检测器，以响应于来自地址转换检测器的控制信号和由第三升压电容器和负载电阻器产生的输出信号产生检测信号，并且时钟控制电路适于使能电荷共享晶体管，并且在从地址转换检测器接收到控制信号和来自电压检测器的检测信号时，禁用第一升压电容器和第二升压电容器中的一个。字线升压电路还包括放电电路，用于在连接到第三升压电容器的节点处放电升压电压。

5. 发明授权

US08471537B2 Low power high voltage regulator for non-volatile memory device 有权
标题翻译：用于非易失性存储器件的低功率高压稳压器
公开(公告)号：US08471537B2
公开(公告)日：2013-06-25
申请号：US12969571
申请日：2010-12-15
申请人： Young Dong Joo
发明人： Young Dong Joo
IPC分类号： G05F1/577 , H02M3/18 , H02M7/00
CPC分类号： G11C16/30 , G11C5/145
摘要： A high-voltage regulator includes a charge pump for generating a high voltage, a voltage regulator for generating a regulated voltage, and an oscillator having an oscillation frequency. The voltage regulator includes an operational amplifier having the high voltage as power supply, a first input, a second input coupled to a voltage reference, and an output. The voltage regulator further includes a first transistor having gate coupled to the output of the operational amplifier, a first terminal coupled to the high voltage and a second terminal coupled to a first voltage divider. The first voltage divider generates a first divided voltage that is coupled to the first input of the operational amplifier. The voltage regulator also includes a second voltage divider for providing a second divided voltage, wherein the second divided voltage controls the oscillator frequency.
摘要翻译：高压调节器包括用于产生高电压的电荷泵，用于产生调节电压的电压调节器和具有振荡频率的振荡器。电压调节器包括具有作为电源的高电压的运算放大器，第一输入端，耦合到电压基准的第二输入端和输出端。电压调节器还包括第一晶体管，其具有耦合到运算放大器的输出的栅极，耦合到高电压的第一端子和耦合到第一分压器的第二端子。第一分压器产生耦合到运算放大器的第一输入端的第一分压。电压调节器还包括用于提供第二分压的第二分压器，其中第二分压控制振荡器频率。

6. 发明授权

US08259507B2 Word line booster for flash memory device 有权
标题翻译：用于闪存设备的字线增强器
公开(公告)号：US08259507B2
公开(公告)日：2012-09-04
申请号：US12259040
申请日：2008-10-27
申请人： Young Dong Joo
发明人： Young Dong Joo
IPC分类号： G11C16/08
CPC分类号： G11C16/30 , G11C16/08
摘要： A nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with a specific voltage as a drive voltage during an operation of the memory device. The word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel to generate a boosting voltage and a first precharge circuit for precharging the first and second boosting capacitors. The word line booster circuit further includes a third boosting capacitor operatively connected to the first and second boosting capacitors via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor when the charge sharing transistor is enabled.
摘要翻译：非易失性存储器件包括存储器单元的行和列的阵列以及与存储器单元相关联的多个字线和位线。存储装置还包括与字线耦合的字线升压电路，用于在存储器件的操作期间提供具有特定电压的选定字线作为驱动电压。字线升压电路包括并联连接的第一升压电容器和第二升压电容器，以产生升压电压，以及用于对第一和第二升压电容器进行预充电的第一预充电电路。字线升压电路还包括通过电荷共享晶体管可操作地连接到第一和第二升压电容器的第三升压电容器，第三升压电容器连接到负载电阻器的一端以在另一端产生输出信号电荷共享晶体管使能时的负载电阻。

7. 发明授权

US06762970B2 Flash memory device 有权
标题翻译：闪存设备
公开(公告)号：US06762970B2
公开(公告)日：2004-07-13
申请号：US10286973
申请日：2002-11-04
申请人： Young Dong Joo
发明人： Young Dong Joo
IPC分类号： G11C1100
CPC分类号： G11C16/30 , G11C16/26
摘要： The present invention relates to a flash memory device for read-out. The flash memory device comprises a pumping circuit for generating a pumping voltage higher than the power supply voltage depending on an enable signal generated when a standby mode, a read-out mode and a power supply voltage are set up, a capacitor for charging the potential depending on the pumping voltage of the pumping circuit, a word line decoder and a bit line decoder for decoding an address signal to select a word line and a bit line of a given cell from the flash memory cell array, and a word line driver and a bit line driver for applying a given voltage depending on an electric charge stored at the capacitor to the word line and the bit line of the selected cell in the flash memory cell array so that a read-out operation is performed. At this time, a voltage depending on the charge stored at the capacitor is applied to the word line driver and the bit line driver in the read-out mode. Therefore, lowering in the read-out speed by loading of the word line can be significantly improved.
摘要翻译：本发明涉及一种用于读出的闪存装置。闪速存储装置包括：泵电路，用于根据在待机模式，读出模式和电源电压建立时产生的使能信号产生高于电源电压的泵浦电压;用于对电位充电的电容器取决于泵送电路的泵浦电压，字线解码器和位线解码器，用于解码地址信号以从闪存单元阵列中选择给定单元的字线和位线，以及字线驱动器和位线驱动器，用于根据存储在电容器上的电荷将闪电存储单元阵列中的所选单元的字线和位线施加给定电压，以便执行读出操作。此时，根据存储在电容器中的电荷的电压在读出模式下被施加到字线驱动器和位线驱动器。因此，通过加载字线可以显着提高读出速度的降低。

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