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1. 发明授权

US06242812B1 CSP pin configuration compatible with TSOP pin configuration 有权
标题翻译： CSP引脚配置与TSOP引脚配置兼容
公开(公告)号：US06242812B1
公开(公告)日：2001-06-05
申请号：US09323837
申请日：1999-06-02
申请人： Joo Sun Choi
发明人： Joo Sun Choi
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L23/50 , H01L24/06 , H01L24/13 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/13 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/00
摘要： The present invention relates to a pin configuration in a highly integrated memory chip; and, more particularly, to a CSP pin configuration which is compatible with a TSOP pin configuration. A CSP semiconductor device according to the present invention comprises: a die pad area formed in the middle of a semiconductor chip; a first ball pad area allocated at a left side of the die pad area, having a ball array having first and second columns; and a second ball pad area allocated at a right side of the die pad area, having a ball array having first and second columns, wherein the first ball pad area includes ball pads which are positioned at a right side of a corresponding TSOP, wherein the second ball pad area includes ball pads which are positioned at a left side of the corresponding TSOP, wherein the first column of the first ball pad area includes even number pins of the corresponding TSOP, which are disposed in order of lower priority, and the second column of the first ball pad area includes odd number pins of the corresponding TSOP, which are disposed in order of lower priority, and wherein the first column of the second ball pad area includes even number pins of the corresponding TSOP, which are disposed in order of higher priority, and the second column of the second ball pad area includes odd number pins of the TSOP, which are disposed in order of higher priority.
摘要翻译：本发明涉及高度集成的存储芯片中的引脚配置; 更具体地说，涉及与TSOP引脚配置兼容的CSP引脚配置。根据本发明的CSP半导体器件包括：形成在半导体芯片中间的管芯焊盘区域; 分配在芯片焊盘区域的左侧的第一球焊盘区域，具有具有第一和第二列的球阵列; 以及分配在芯片焊盘区域的右侧的第二球焊盘区域，具有具有第一和第二列的球阵列，其中第一球垫区域包括位于相应TSOP右侧的球垫，其中，第二球垫区域包括位于相应TSOP的左侧的球垫，其中第一球垫区域的第一列包括相应TSOP的偶数针，其按优先级顺序排列，第二球垫所述第一球焊盘区域的列包括相应TSOP的奇数引脚，其以较低优先级的顺序布置，并且其中第二球焊盘区域的第一列包括相应的TSOP的偶数引脚，其按顺序布置并且第二球焊盘区域的第二列包括以较高优先级的顺序设置的TSOP的奇数引脚。

2. 发明授权

US5886932A Composite mode substrate voltage generation circuit for dynamic random access memory 失效
标题翻译：用于动态随机存取存储器的复合模式衬底电压产生电路
公开(公告)号：US5886932A
公开(公告)日：1999-03-23
申请号：US966192
申请日：1997-11-07
申请人： Joo Sun Choi
发明人： Joo Sun Choi
IPC分类号： G11C11/407 , G05F3/20 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/4074 , G11C11/408 , H01L21/8242 , H01L27/108 , G11C16/04
CPC分类号： G05F3/205 , G11C11/4074 , G11C5/146
摘要： A composite mode substrate voltage generation circuit for a DRAM which has a memory cell block and a peripheral circuit block formed on a single substrate. The circuit comprises a back-bias voltage generator for generating a first back-bias voltage in response to a normal refresh mode control signal or a second back-bias voltage in response to a self-refresh mode control signal and supplying the generated first or second back-bias voltage to the memory cell and peripheral circuit blocks, a first voltage level detector for detecting a level of the first back-bias voltage from the back-bias voltage generator, comparing the detected level of the first back-bias voltage with a first reference voltage level and controlling a voltage pumping operation of the back-bias voltage generator in accordance with the compared result, and a second voltage level detector for detecting a level of the second back-bias voltage from the back-bias voltage generator, comparing the detected level of the second back-bias voltage with a second reference voltage level and controlling the voltage pumping operation of the back-bias voltage generator in accordance with the compared result. A self-refresh operation can stably be performed at low power consumption, resulting in an increase in refresh efficiency of the DRAM.
摘要翻译：一种用于DRAM的复合模式衬底电压产生电路，其具有形成在单个衬底上的存储单元块和外围电路块。电路包括背偏置电压发生器，用于响应于自刷新模式控制信号响应于正常的刷新模式控制信号或第二反向偏置电压而产生第一反偏压，并将产生的第一或第二对所述存储单元和外围电路块的反向偏置电压;第一电压电平检测器，用于检测来自所述背偏电压发生器的所述第一反向偏置电压的电平，将所检测到的所述第一背偏电压的电平与第一参考电压电平，并且根据比较结果控制背偏置电压发生器的电压抽运操作;以及第二电压电平检测器，用于检测来自背偏电压发生器的第二反偏压电平的电平，比较检测到具有第二参考电压电平的第二背偏电压的电平，并且根据机智控制背偏置电压发生器的电压抽运操作 h比较结果。可以在低功耗下稳定地执行自刷新操作，导致DRAM的刷新效率的提高。

3. 发明授权

US06286077B1 Synchronous semiconductor memory device with a plurality of memory modules which has an additional function for masking a data strobe signal outputted from each memory module 失效
标题翻译：具有多个存储器模块的同步半导体存储器件，其具有用于屏蔽从每个存储器模块输出的数据选通信号的附加功能
公开(公告)号：US06286077B1
公开(公告)日：2001-09-04
申请号：US09218617
申请日：1998-12-22
申请人： Joo Sun Choi , Seok Cheol Yoon
发明人： Joo Sun Choi , Seok Cheol Yoon
IPC分类号： G06F1200
CPC分类号： G11C7/1066 , G11C7/1006
摘要： A chip set memory controller having a data strobe mask function is disclosed. The controller includes first through N-th memory modules operated in synchronous with a clock signal outputted from the chip set memory controller, whereby the data outputted from each memory module are masked by a data mask signal outputted from the chip set memory controller, and the operation of the data outputted from each memory module is controlled by a data strobe signal outputted from each memory module, for thereby implementing a reverse compatibility of a DQM function by additionally installing a pin in a DDR SDRAM and masking a data strobe signal.
摘要翻译：公开了具有数据选通掩模功能的芯片组存储器控制器。控制器包括与从芯片组存储器控制器输出的时钟信号同步操作的第一至第N存储器模块，由此从每个存储器模块输出的数据由芯片组存储器控制器输出的数据屏蔽信号屏蔽，从每个存储器模块输出的数据的操作由每个存储器模块输出的数据选通信号控制，从而通过在DDR SDRAM中额外安装引脚并屏蔽数据选通信号来实现DQM功能的反向兼容性。

4. 发明授权

US06240033B1 Antifuse circuitry for post-package DRAM repair 有权
标题翻译：用于后封装DRAM修复的防漏电路
公开(公告)号：US06240033B1
公开(公告)日：2001-05-29
申请号：US09479665
申请日：2000-01-10
申请人： Woodward Yang , Joo Sun Choi , Jae Kyung Wee , Young Ho Seol , Jin Keun Oh , Phil Jung Kim , Ho Youe Cho
发明人： Woodward Yang , Joo Sun Choi , Jae Kyung Wee , Young Ho Seol , Jin Keun Oh , Phil Jung Kim , Ho Youe Cho
IPC分类号： G11C700
CPC分类号： G11C29/781 , G11C17/18
摘要： The anti-fuse circuit includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses; a programming voltage generator consisting of an oscillator and a charge pump; and an anti-fuse unit circuits for the program/read of anti-fuse states. For an anti-fuse program at the special test mode, a program address generation circuit having inputs of control signals and addresses activates the programming voltage generator and makes a special or program address for selection of anti-fuse. In the normal mode, the program address generation circuit and an internal power generator remain at an inactive state. In anti-fuse unit circuit, the program address and the programming voltage signal from the programming voltage generator serve to switch the terminal of the anti-fuse up to a programming voltage level when the anti-fuse is selected for programming of anti-fuse elements.
摘要翻译：反熔丝电路包括三个子块：具有控制信号和地址的输入并产生编程信号和程序地址的激活的多路复用器; 由振荡器和电荷泵组成的编程电压发生器; 以及用于编程/读取反熔丝状态的反熔丝单元电路。对于在特殊测试模式下的反熔丝程序，具有控制信号和地址的输入的程序地址产生电路激活编程电压发生器，并产生用于选择反熔丝的特殊或程序地址。在正常模式中，程序地址产生电路和内部发电机保持在非工作状态。在反熔丝单元电路中，编程电压发生器的程序地址和编程电压信号用于在反熔丝被选择用于编程抗熔丝元件时将反熔丝的端子切换到编程电压电平。

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