专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08923014B2 Display device having touch panel 有权
标题翻译：具有触摸面板的显示装置
公开(公告)号：US08923014B2
公开(公告)日：2014-12-30
申请号：US13209169
申请日：2011-08-12
申请人： Jong-Hyuk Kim , Joong-Lok Song
发明人： Jong-Hyuk Kim , Joong-Lok Song
IPC分类号： H05K9/00 , G06F3/041 , G06F3/044
CPC分类号： G06F3/0418 , G06F3/044 , G06F2203/04107
摘要： A display device having a touch panel which effectively intercepts noise generated from a display panel to prevent the touch panel from malfunctioning. The display device having the touch panel includes a display panel, a touch panel attached to the display panel through an adhesion layer, a noise interception layer over an entire rear surface of the touch panel to prevent electrical noise from the display panel from being introduced into the touch panel, a metal ring pattern on the noise interception layer to surround the edge of the noise interception layer and having lower electrical resistance than the noise interception layer, and a ground terminal electrically connected to the noise interception layer and the metal ring pattern.
摘要翻译：一种具有触摸面板的显示装置，其有效地拦截从显示面板产生的噪声，以防止触摸面板发生故障。具有触摸面板的显示装置包括显示面板，通过粘合层附着到显示面板的触摸面板，在触摸面板的整个后表面上的噪声截取层，以防止来自显示面板的电噪声被引入所述触摸面板，所述噪声截取层上的围绕所述噪声截取层的边缘并且具有比所述噪声截取层更低的电阻的金属环图案，以及电连接到所述噪声截取层和所述金属环图案的接地端子。

2. 发明授权

US08759224B2 Method of forming a pattern structure for a semiconductor device 有权
标题翻译：形成半导体器件的图案结构的方法
公开(公告)号：US08759224B2
公开(公告)日：2014-06-24
申请号：US13212349
申请日：2011-08-18
申请人： Jong-Hyuk Kim , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
发明人： Jong-Hyuk Kim , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76816
摘要： In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.
摘要翻译：在形成图案结构的方法中，通过使用牺牲掩模图案和掩模图案的连接部分的双重图案化工艺来形成半导体器件的节点分离线的截止部分，从而提高对准边缘。掩模图案和牺牲掩模图案之间的对准边缘增加到牺牲掩模图案的连接部分的长度的量。与节点分离线相邻的线包括向分离线的截止部分突出的突出部分。

3. 发明授权

US08171841B2 Detachable connecting rod and compressor having the same 有权
标题翻译：具有相同的可拆卸连杆和压缩机
公开(公告)号：US08171841B2
公开(公告)日：2012-05-08
申请号：US12226676
申请日：2006-12-29
申请人： Kyoung-Jun Park , Ji-Young Bae , Jin-Kook Kim , Bum-Joon Kim , Hyuk Nam , Jong-Mok Lee , Jong-Hyuk Kim , Kyeong-Ho Kim
发明人： Kyoung-Jun Park , Ji-Young Bae , Jin-Kook Kim , Bum-Joon Kim , Hyuk Nam , Jong-Mok Lee , Jong-Hyuk Kim , Kyeong-Ho Kim
IPC分类号： F01B29/00 , F01B9/00
CPC分类号： F04B39/0022 , F16C2360/42 , Y10T74/2142 , Y10T74/2162
摘要： A detachable connecting rod includes a first member (410)a large end portion (411) having a trough hole (H1), and a first connection rod portion (412) extending from the large end portion (411), the first connection rod portion (412) having a pair of spaced apart arms defining a coupling groove (413) extending in the same direction as an axial direction of the through hole (H1); a second member (420) including a small end portion having a through hole (H2), and second connection rod portion (422) extending from the small end portion, the second connection rod (422) portion being inserted into the coupling groove (413) and a coupling unit for coupling the first connection rod portion (412) to the second connection rod portion inserted (412) into the coupling groove (413) of the first member (410). The detachable connecting rod is useable in a compressor.
摘要翻译：一种可拆卸的连接杆包括：第一部件（410），具有槽孔（H1）的大端部（411）和从大端部（411）延伸的第一连接杆部分（412），第一连接杆部分（412），其具有限定沿与所述通孔（H1）的轴向方向相同的方向延伸的联接槽（413）的一对间隔开的臂。包括具有通孔（H2）的小端部的第二构件（420）和从所述小端部延伸的第二连接杆部分（422），所述第二连接杆（422）部分插入所述联接槽（413））和用于将第一连接杆部分（412）连接到插入（412）的第二连接杆部分到第一部件（410）的联接槽（413）中的联接单元。可拆卸连杆可用于压缩机。

4. 发明申请

US20090233405A1 METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES 有权
标题翻译：形成NAND型非易失性存储器件的方法
公开(公告)号：US20090233405A1
公开(公告)日：2009-09-17
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

5. 发明授权

US07554140B2 Nand-type non-volatile memory device 失效
标题翻译： Nand型非易失性存储器件
公开(公告)号：US07554140B2
公开(公告)日：2009-06-30
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L31/062
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

6. 发明申请

US20080149021A1 Methods of Forming Dual Damascene Structures 失效
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US20080149021A1
公开(公告)日：2008-06-26
申请号：US12043576
申请日：2008-03-06
申请人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
发明人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
IPC分类号： C30B25/02
CPC分类号： H01L21/76876 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28525 , H01L21/28562 , H01L21/76808 , H01L21/76831 , H01L21/76879 , H01L21/76895 , H01L29/66477 , Y10T428/24331
摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
摘要翻译：公开了一种双镶嵌结构和形成双镶嵌结构的方法。双镶嵌结构包括绝缘构件，单晶构件和填充构件。绝缘构件具有双镶嵌形状的开口。填充构件形成在开口的侧面上。单晶构件接触填充构件。单晶构件填充开口。为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。填充构件形成在开口的侧面上。外延的初步单晶构件生长以填满开口。由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

7. 发明申请

US20100167498A1 SUBSTRATE LEVEL BONDING METHOD AND SUBSTRATE LEVEL PACKAGE 有权
标题翻译：衬底水平焊接方法和衬底层封装
公开(公告)号：US20100167498A1
公开(公告)日：2010-07-01
申请号：US12646691
申请日：2009-12-23
申请人： Chul-Soo KIM , Kuk-Jin Chun , Sung-Chan Kang , Jong-Hyuk Kim , In-Sang Song , Duck-Hwan Kim , Jae-Shik Shin
发明人： Chul-Soo KIM , Kuk-Jin Chun , Sung-Chan Kang , Jong-Hyuk Kim , In-Sang Song , Duck-Hwan Kim , Jae-Shik Shin
IPC分类号： H01L21/50
CPC分类号： H01L23/10 , H01L21/50 , H01L21/76898 , H01L25/50 , H01L27/14601 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are a substrate level bonding method and a substrate level package formed thereby. The substrate level package includes a plurality of unit substrate sections, a base substrate, and a plurality of substrate adhesion sections. The unit substrate sections are separated from each other by holes. The base substrate is disposed to face the unit substrate sections. The substrate adhesion sections are interposed between the unit substrate sections and the base substrate to bond the unit substrate sections to the base substrate and which are formed of DFR material, whose at least one portion is uncured.
摘要翻译：公开了一种由此形成的衬底水平焊接方法和衬底层封装。基板级封装包括多个单元基板部分，基底基板和多个基板粘合部分。单元基板部分通过孔彼此分离。基底基板设置成面对单元基板部分。基板粘合部分插入在单元基板部分和基底基板之间，以将单元基板部分粘合到基底基板上，并且由至少一部分未固化的DFR材料形成。

8. 发明授权

US07589375B2 Non-volatile memory devices including etching protection layers and methods of forming the same 有权
标题翻译：包括蚀刻保护层的非易失性存储器件及其形成方法
公开(公告)号：US07589375B2
公开(公告)日：2009-09-15
申请号：US11642297
申请日：2006-12-20
申请人： Jae-Hoon Jang , Soon-Moon Jung , Jong-Hyuk Kim , Young-Seop Rah , Han-Byung Park
发明人： Jae-Hoon Jang , Soon-Moon Jung , Jong-Hyuk Kim , Young-Seop Rah , Han-Byung Park
IPC分类号： H01L27/115
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/105 , H01L27/1116
摘要： A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.
摘要翻译：非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。

9. 发明申请

US20080085582A1 Hand-type nonvolatile memory device and method of forming the same 失效
标题翻译：手持式非易失性存储装置及其形成方法
公开(公告)号：US20080085582A1
公开(公告)日：2008-04-10
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

10. 发明授权

US07276404B2 Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns 有权
公开(公告)号：US07276404B2
公开(公告)日：2007-10-02
申请号：US11589618
申请日：2006-10-30
申请人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
发明人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1108 , Y10S257/903
摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式