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1. 发明授权

US06760838B2 System and method of initializing and determining a bootstrap processor [BSP] in a fabric of a distributed multiprocessor computing system 有权
标题翻译：在分布式多处理器计算系统的结构中初始化和确定引导处理器[BSP]的系统和方法
公开(公告)号：US06760838B2
公开(公告)日：2004-07-06
申请号：US09773763
申请日：2001-01-31
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
IPC分类号： G06F15177
CPC分类号： G06F15/177
摘要： A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed. This scheme includes designating a bootstrap processor, locating the boot ROM, establishing the manner in which the devices are interconnected, and defining routing directions for routing communications among the various devices in the computing system.
摘要翻译：提供了一种用于初始化包括在包括多个独立点对点链路的通信链路上通信的多个设备的计算系统的方法，每个点对点链路互连所述多个设备中的相应对。该方法包括链路初始化过程，其包括首先使用包括公共频率和公共链路宽度的公共通信参数在每个互连链路上配置每个相应设备对进行通信。链路初始化过程还可以包括用于确定每个互连的设备对的最大通信参数的优化过程。如果最大兼容参数与任何设备对的公共参数不同，则可以使用最大兼容参数将该对设备重新配置为在互连链路上进行通信。一旦建立了通信能力，就可以执行用于计算机系统的一个或多个通信结构的建立。该方案包括指定引导处理器，定位引导ROM，建立设备互连的方式，以及定义用于在计算系统中的各种设备之间路由通信的路由选择方向。

2. 发明授权

US06745272B2 System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system 有权
标题翻译：增加带宽的系统和方法，用于将有序交易发布到分布式通信系统中
公开(公告)号：US06745272B2
公开(公告)日：2004-06-01
申请号：US09826262
申请日：2001-04-04
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
IPC分类号： G06F1300
CPC分类号： H04L1/1671
摘要： A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.
摘要翻译：一种将一对有序请求的第二请求发布到分布式相干通信结构中的方法和系统。有序对的第一个请求被发布到相干通信结构中，并被引导到第一个目标。将第二个请求发送到相干通信结构中停止，直到第一个目标接收并订购第一个请求并发送确认该响应的响应。

3. 发明授权

US07069361B2 System and method of maintaining coherency in a distributed communication system 有权
公开(公告)号：US07069361B2
公开(公告)日：2006-06-27
申请号：US09840449
申请日：2001-04-23
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
IPC分类号： G06F13/00
CPC分类号： H04L1/1671
摘要： A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.

4. 发明授权

US07640315B1 Implementing locks in a distributed processing system 有权
标题翻译：在分布式处理系统中实现锁定
公开(公告)号：US07640315B1
公开(公告)日：2009-12-29
申请号：US09633087
申请日：2000-08-04
申请人： Derrick R. Meyer , Jonathan M. Owen , Mark D. Hummel , James B. Keller
发明人： Derrick R. Meyer , Jonathan M. Owen , Mark D. Hummel , James B. Keller
IPC分类号： G06F15/16
CPC分类号： G06F9/52
摘要： A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto. After completion of lock operations, the lock requesting node sends a lock release request to the arbitrating node, which, in turn, informs all processing nodes of lock release by transmitting another broadcast message within the system. The messaging protocol is completed when each node sends another probe response to the arbitrating node, which, in turn, sends a final target done message to the lock requesting node. Lock operations are performed without contention for system resources and without deadlocks among various processing nodes.
摘要翻译：用于使具有使用双向单向链路的互连结构互连的两个或多个处理节点的分布式存储器多处理计算机系统内的进程同步的消息传递方案。每个单向链路形成点对点互连以在两个处理节点之间传送分组信息。当没有先前的锁定请求正在等待服务时，来自锁定请求节点的锁定获取请求被仲裁节点投入使用。仲裁节点向系统中的所有节点发送广播消息，后者又响应相应的探测响应消息，通知仲裁节点发送探测响应消息的节点发出新请求。仲裁节点通过向其发送目标完成消息来向锁请求节点通知请求节点的锁拥有权。锁定操作完成后，锁定请求节点向仲裁节点发送锁定释放请求，仲裁节点又通过在系统内传送另一个广播消息来通知所有处理节点的锁定释放。当每个节点向仲裁节点发送另一个探测响应时，完成消息协议，该仲裁节点又向锁定请求节点发送最终的目标完成消息。执行锁定操作而不对系统资源产生争用，并且在各种处理节点之间没有死锁。

5. 发明授权

US06665742B2 SYSTEM FOR RECONFIGURING A FIRST DEVICE AND/OR A SECOND DEVICE TO USE A MAXIMUM COMPATIBLE COMMUNICATION PARAMETERS BASED ON TRANSMITTING A COMMUNICATION TO THE FIRST AND SECOND DEVICES OF A POINT-TO-POINT LINK 有权
标题翻译：用于重新配置第一设备和/或第二设备的系统，以便基于向点到点链路的第一和第二设备发送通信来使用最大的兼容通信参数
公开(公告)号：US06665742B2
公开(公告)日：2003-12-16
申请号：US09773777
申请日：2001-01-31
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
IPC分类号： G06F1310
CPC分类号： H04L29/06 , H04L69/24
摘要： A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed.
摘要翻译：提供了一种用于初始化包括在包括多个独立点对点链路的通信链路上通信的多个设备的计算系统的方法，每个点对点链路互连所述多个设备中的相应对。该方法包括链路初始化过程，其包括首先使用包括公共频率和公共链路宽度的公共通信参数在每个互连链路上配置每个相应设备对进行通信。链路初始化过程还可以包括用于确定每个互连的设备对的最大通信参数的优化过程。如果最大兼容参数与任何设备对的公共参数不同，则可以使用最大兼容参数将该对设备重新配置为在互连链路上进行通信。一旦建立了通信能力，就可以执行用于计算机系统的一个或多个通信结构的建立。

6. 发明授权

US06751684B2 System and method of allocating bandwidth to a plurality of devices interconnected by a plurality of point-to-point communication links 失效
标题翻译：将带宽分配给由多个点对点通信链路互连的多个设备的系统和方法
公开(公告)号：US06751684B2
公开(公告)日：2004-06-15
申请号：US09746109
申请日：2000-12-21
申请人： Jonathan M. Owen , Mark D. Hummel
发明人： Jonathan M. Owen , Mark D. Hummel
IPC分类号： G06F300
CPC分类号： H04L47/30 , H04L47/10 , H04L47/22
摘要： A method is provided for fairly allocating bandwidth to a plurality of devices connected to a communication link implemented as a plurality of point-to-point links. The point-to-point links interconnect the devices in a daisy chain fashion. Each device is configured to transmit locally generated packets and to forward packets received from downstream devices onto one of the point-to-point links. The rate at which each device transmits local packets relative to forwarding received packets is referred to as the device's insertion rate. A fair bandwidth allocation algorithm is implemented in each (upstream) device to determine the highest packet issue rate of the devices which are downstream of that (upstream) device. The packet issue rate of a downstream device is the number of local packets associated with the downstream device that are received at the upstream device relative to the total number of packets received at the upstream device. By monitoring the total flow of packets received at the upstream device, the highest packet issue rate of the respective packet issue rates of the downstream devices may be determined. Each upstream device then matches its insertion rate to the highest packet issue rate of its downstream devices. The determination of the highest packet issue rate may be performed dynamically such that the insertion rate of the upstream device can adapt to changes in communication traffic patterns. Further, the fair bandwidth allocation algorithm may include a priority algorithm to arbitrate between local and received packets transmitted at the insertion rate.
摘要翻译：提供了一种方法，用于向连接到实现为多个点对点链路的通信链路的多个设备公平地分配带宽。点对点链路以菊花链方式互连设备。每个设备被配置为发送本地生成的分组，并将从下游设备接收的分组转发到点对点链路之一。每个设备相对于转发接收的分组传输本地分组的速率被称为设备的插入速率。在每个（上游）设备中实现公平的带宽分配算法，以确定在（上游）设备下游的设备的最高分组发布速率。下游设备的报文发布速率是与上游设备接收的下游设备相关联的本地报文数量，相对于上游设备接收的报文总数。通过监视在上游设备接收的分组的总流量，可以确定下游设备的相应分组发布速率的最高分组发布速率。然后，每个上游设备将其插入速率与其下游设备的最高分组发布速率相匹配。可以动态地执行最高分组发布速率的确定，使得上游设备的插入速率可以适应通信业务模式的变化。此外，公平带宽分配算法可以包括优先级算法，以在插入速率下发送的本地和接收分组之间进行仲裁。

7. 发明授权

US06721813B2 Computer system implementing a system and method for tracking the progress of posted write transactions 有权
标题翻译：计算机系统实现跟踪发布的写事务进度的系统和方法
公开(公告)号：US06721813B2
公开(公告)日：2004-04-13
申请号：US09774148
申请日：2001-01-30
申请人： Jonathan M. Owen , Mark D. Hummel , James B. Keller
发明人： Jonathan M. Owen , Mark D. Hummel , James B. Keller
IPC分类号： G06F1300
CPC分类号： G06F13/4243
摘要： A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction. The I/O node may dispatch the non-coherent write transaction directed to the host bridge. The host bridge may respond to the non-coherent write transaction by translating the non-coherent write transaction to a coherent write transaction, and dispatching the coherent write transaction to the second processing node. The second processing node may respond to the coherent write transaction by dispatching a target done response directed to the host bridge.
摘要翻译：提出了一种实现用于跟踪已发布的写入事务进度的系统和方法的计算机系统。在一个实施例中，计算机系统包括处理子系统和输入/输出（I / O）子系统。处理子系统包括通过相干通信链路互连的多个处理节点。每个处理节点可以包括优选执行软件指令的处理器。 I / O子系统包括一个或多个I / O节点。每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。多个处理节点可以包括第一处理节点和第二处理节点，其中第一处理节点包括主机桥，并且其中存储器耦合到第二处理节点。 I / O节点可以生成非相干写事务以在第二处理节点的存储器内存储数据，其中非相干写事务是已发布的写事务。 I / O节点可以调度定向到主桥的非相干写入事务。主桥可以通过将非相干写事务转换为相干写事务来响应非相干写事务，并将相干写事务分派到第二处理节点。第二处理节点可以通过调度定向到主桥的目标完成响应来响应相干写事务。

8. 发明授权

US06950438B1 System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system 有权
标题翻译：用于在多处理器计算机系统中实现用于发布请求的单独虚拟通道的系统和方法
公开(公告)号：US06950438B1
公开(公告)日：2005-09-27
申请号：US09640602
申请日：2000-08-17
申请人： Jonathan M. Owen , Mark D. Hummel , James B. Keller
发明人： Jonathan M. Owen , Mark D. Hummel , James B. Keller
IPC分类号： H04L12/00 , H04L29/06
CPC分类号： H04L69/12
摘要： A computer system employs virtual channels and allocates different resources to the virtual channels. More particularly, the computer system provides a posted commands virtual channel separate from the non-posted commands virtual channel for routing posted and non-posted commands or requests through coherent and noncoherent fabrics within the computer system. Because separate resources are allocated to the virtual channels in the computer system, posted requests may be allowed to become unordered with other requests from the same source. Implementation of a separate posted commands virtual channel may allow the computer system to maintain compatibility with I/O systems in which posted write requests may become unordered with previous posted requests (e.g., the Peripheral Component Interconnect Bus, or PCI). Implementation of the separate posted commands virtual channel thus may assist in providing deadlock-free operation.
摘要翻译：计算机系统采用虚拟通道并为虚拟通道分配不同的资源。更具体地，计算机系统提供与非发布的命令虚拟通道分离的已发布命令虚拟通道，用于通过计算机系统内的相干和非相干结构路由发布和未发布的命令或请求。因为单独的资源被分配给计算机系统中的虚拟通道，所以可能允许发布的请求变得与来自相同源的其他请求无序。单独发布的命令虚拟通道的实现可以允许计算机系统保持与I / O系统的兼容性，其中发布的写入请求可能与先前发布的请求（例如，外围组件互连总线或PCI）无序。单独发布的命令虚拟通道的实现可能有助于提供无死锁操作。

9. 发明申请

US20110283124A1 METHOD AND APPARATUS FOR CACHE CONTROL 有权
标题翻译：缓存控制的方法和设备
公开(公告)号：US20110283124A1
公开(公告)日：2011-11-17
申请号：US12777657
申请日：2010-05-11
申请人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
发明人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
摘要翻译：公开了一种用于动态控制高速缓存大小的方法和装置。在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

10. 发明申请

US20080288799A1 DYNAMIC PROCESSOR POWER MANAGEMENT DEVICE AND METHOD THEREOF 有权
标题翻译：动态处理器电源管理装置及其方法
公开(公告)号：US20080288799A1
公开(公告)日：2008-11-20
申请号：US11750365
申请日：2007-05-18
申请人： Alex Branover , Frank P. Helms , Jonathan M. Owen , Kurt Lewchuk , Maurice Steinman , Paul Mackey
发明人： Alex Branover , Frank P. Helms , Jonathan M. Owen , Kurt Lewchuk , Maurice Steinman , Paul Mackey
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.
摘要翻译：处理器可以在不同的功率模式下工作。在有功功率模式下，处理器执行软件。响应于从软件接收到停止指示，处理器处的硬件评估处理器的总线事务。如果总线事务满足启发式，则硬件将处理器内核置于较低功耗模式下，例如保留模式。由于总线事务由硬件而不是软件进行评估，并且软件不需要执行握手和其他协议来将处理器置于低功耗模式，处理器能够将处理器内核置于低功耗模式更快，从而节约电力。

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